2. PLD (Programmable Logic Device) Wednesday, October 07, 2015 1 ARINDAM CHAKRABORTY LECTURER,DEPT. OF ECE INSTITUTE OF ENGINEERING & MANAGEMENT

4. COMPLEXITY 1905 : Mount Road -Madras2005: Mount Road -Madras

5. Integrated Circuit Revolution 1958:First integrated circuit (germanium) Built by Jack Kilbyat Texas Instruments components :Transistors, Resistors and Capacitors 2000: Intel Pentium 4 Processor Clock speed: 1.5 GHz Transistors: 42 million Technology: 0.18μm CMOS

6. If Transistors are Counted as Seconds

7. Evolution of VLSI SSI–Small Scale Integration (GATE < 10 ) MSI–Medium Scale Integration (10 < GATE < 1000) Demanded automation of design process Computer Aid Design started evolving LSI–Large Scale Integration (GATE > 1000) VLSI–Very Large Scale Integration ( GATE > 100000)

8. Before Tools Laid out 4004 by hand –Drawn on paper and photographed –Demagnified 500 times smaller Almost no verification or validation –Chips may not function properly –Market may return products SOLUTION !

9. VLSI chip design forced Automation of process Automation of Simulation based verification REPLACING Breadboard Techniques HDL Development Evolution of CAD Tools

10. Comparison of Sizes

11. How Small Are The Transistors?

12. Processor Power Trends

13. Evolution in IC Complexity

14. Design Goals Over Time

15. COMPLEXITY 1905 : Mount Road -Madras2005: Mount Road -Madras

16. ROM F1F1 F2F2 A B CiCi  SIZE OF ROM:- FOR, ‘n’ No. OF INPUT AND ‘m’ No. OF OUTPUT SIZE =2 n x m BITS  SIZE OF ROM:- FOR, ‘n’ No. OF INPUT AND ‘m’ No. OF OUTPUT SIZE =2 n x m BITS  IT IS TRUTH TABLE IN A HARDWARE FORM OR WE CAN SAY HARDWARE FOR TRUTH TABLE  IT IS TRUTH TABLE IN A HARDWARE FORM OR WE CAN SAY HARDWARE FOR TRUTH TABLE ‘n’ ‘m’ ROM Read Only Memory (ROM) Wednesday, October 07, 2015 15

17. DECODER (AND ARRAY) m0m0 m1m1 m2m2 m3m3 m4m4 m5m5 m6m6 m7m7 aiai bibi C i-1 Si Ci DECODER DESIGN APPLYING 1-BIT FULL ADDER Si = F (1,2,4,7) Ci = F (3,5,6,7) Wednesday, October 07, 2015 16 Read Only Memory (ROM)

18. Read only memory (ROM) ROM holds programs and data permanently even when computer is switched off Data can be read by the CPU in any order so ROM is also direct access The contents of ROM are fixed at the time of manufacture Access time of between 10 and 50 nanoseconds

20. Wednesday, October 07, 2015 19 PROGRAMMABLE :: I CAN CHANGE THE APPLICATION LOGIC :: THE VALIDITY OF AN ARGUMENT IS DETERMINED BY ITS LOGICAL FORM DEVICE :: MACHINE PLD

21. Wednesday, October 07, 2015 20 Programmable Logic Device(PLD): user configurable A programmable logic devices is an IC’s that user configurable implementing and is capable of implementing logic function PLDs ARE :- I. COMBINATIONAL PLDs II. SEQUENTIAL PLDs

22. Wednesday, October 07, 2015 21 I. COMBINATIONAL PROGRAMMABLE LOGIC DEVICE (PLD):

23. DIFFERENT TYPES OF COMBINATIONAL PLDs :- Fixed AND Array (Decoder) Programmable OR Array Input Output A. Programmable Read Only Memory (PROM) : Programmable AND Array Fixed OR Array Input Output B. Programmable Array Logic (PAL) : Programmable AND Array Programmable OR Array Input Output C. Programmable Logic Array (PLA) : Wednesday, October 07, 2015 22

24. DIFFERENT TYPEs OF ROM:- ROM (AND & OR ARRAY BOTH ARE FIXED) PROM (FIXED AND ARRAY & PROGRAMMABLE OR ARRAY) EPROM (ERASABLE PROM> TO CHANGE MORE TIME) UVEPROM (OLD TECH.> TO CHANGE THE LOGIC USING UV RAY) EEPROM(ELECTRICALLY ERASABLE PROM> APPLYING ELEC. PULSES) EAPROM(ELECTRICALLY ALTERABLE PROM> NEW TECH) OR FLASH MEMORY Wednesday, October 07, 2015 23

25. Types of ROM 1. Programmable Read Only Memory (PROM) Empty of data when manufactured May be permanently programmed by the user 2. Erasable Programmable Read Only Memory (EPROM) Can be programmed, erased and reprogrammed The EPROM chip has a small window on top allowing it to be erased by shining ultra-violet light on it After reprogramming the window is covered to prevent new contents being erased Access time is around 45 – 90 nanoseconds Note: a nanosecond is one billionth of a second!

26. Types of ROM 3. Electrically Erasable Programmable Read Only Memory (EEPROM) Reprogrammed electrically without using ultraviolet light Must be removed from the computer and placed in a special machine to do this Access times between 45 and 200 nanoseconds 4. Flash ROM Similar to EEPROM However, can be reprogrammed while still in the computer Easier to upgrade programs stored in Flash ROM Used to store programs in devices Access time is around 45 – 90 nanoseconds Note: a nanosecond is one billionth of a second!

27. DIFFERENT TYPEs OF ROM:- Wednesday, October 07, 2015 26

28. DIFFERENT TYPES OF COMBINATIONAL PLDs :- Fixed AND Array (Decoder) Programmable OR Array Input Output A. Programmable Read Only Memory (PROM) :

29. AND ARRAY m0m0 m1m1 m2m2 m3m3 m4m4 m5m5 m6m6 m7m7 aiai bibi C i-1 SiCi OR ARRAY FIXED AND ARRAY & PROGRAMMABLE OR ARRAY APPLYING 1-BIT FULL ADDER Si = F (1,2,4,7) Ci = F (3,5,6,7) (A) Programmable Read Only Memory (PROM)Wednesday, October 07, 2015 28

30. Programmable AND Array Fixed OR Array Input Output B. Programmable Array Logic (PAL) : DIFFERENT TYPES OF COMBINATIONAL PLDs :-

31. ( B) PROGRAMMABLE ARRARY LOGIC ( PAL ) :- XYZ F1F3 P0 F1= XY + X’Z F2= Y’ + X’Z F3= XY + Y’Z Wednesday, October 07, 2015 30 P1 P2 P3 P4 P5 P0P1 P2 P3 P4 P5 PAL F2 PROGRAMMABLE AND ARRAY & FIXED OR ARRAY

32. PAL Table (Specifications): SIZE OF PAL :  3 INPUTs  3 OUTPUT  6 PRODUCT TERM  2 FOR EACH OUTPUT P0P1P2P3P4P5 F1YESYESNILNILNILNIL F2NILNILYESYESNILNIL F3NILNILNILNILYESYES

33. Programmable AND Array Array Programmable OR Array Input Output C. Programmable Logic Array (PLA) : DIFFERENT TYPES OF COMBINATIONAL PLDs :-

34. AND ARRAY P0P0 P1P1 P2P2 P3P3 A B C F1F1 F2F2 OR ARRAY PROGRAMMABLE AND ARRAY & PROGRAMMABLE OR ARRAY ( C ) PROGRAMMABLE LOGIC ARRARY ( PLA ) :- PRODUCT TERM Wednesday, October 07, 2015 33

35. ( C) PROGRAMMABLE LOGIC ARRARY ( PLA ) :- XYZ F1 F2 F3 P0 P1 P2 P3 F1= XY + X’Z F2= Y’ + X’Z F3= XY + Y’Z P0P0 P1P1 P3P3 P2P2 Wednesday, October 07, 2015 34 PLA P0P0 P1P1 PROGRAMMABLE AND ARRAY & PROGRAMMABLE OR ARRAY

36. PLA Table (Specifications): SIZE OF PLA :  3 3 3 3 INPUTs  4 4 4 4 PRODUCT TERM  3 3 3 3 OUTPUT

37. Design PAL : PAL Table (Specifications): SIZE OF PAL :  3 INPUTs  6 PRODUCT TERM  3 OUTPUT  2 FOR EACH OUTPUT P0P1P2P3P4P5 F1YESYESNILNILNILNIL F2NILNILYESYESNILNIL F3NILNILNILNILYESYES F1(a,b,c) = ∑m (0,2) F2(a,b,c) = ∑m (0,3,4) F3(a,b,c) = ∑m (0,3,4,7)

38. Design PLA : PLA Table (Specifications): SIZE OF PLA :  3 INPUTs  6 PRODUCT TERM  3 OUTPUT P0P1P2P3P4P5 F1YESNILNILNILNILNIL F2NILYESYESNILNILNIL F3NILNILNILYESYESNIL F1(a,b,c) = ∑m (0,2) F2(a,b,c) = ∑m (0,3,4) F3(a,b,c) = ∑m (0,3,4,7)

39. Programmable Array Logic (PAL) & Programmable Logic Array (PLA) : Wednesday, October 07, 2015 38

40. Wednesday, October 07, 2015 39 II. SEQUENTIAL PROGRAMMABLE LOGIC DEVICE (PLD):

41. DIFFERENT TYPES OF SEQUENTIAL PLDs :- A. SIMPLE PROGRAMMABLE LOGIC DEVICE (SPLD) : B. COMPLEX PROGRAMMABLE LOGIC DEVICE (CPLD): C. FIELD PROGRAMMABLE GATE ARRAY (FPGA) : Wednesday, October 07, 2015 40

42. Wednesday, October 07, 2015 41 (I) SIMPLE PROGRAMMABLE LOGIC DEVICE (SPLD) :: INPUT OUTPUT An SPLD can implement hundreds of gates An SPLD can implement hundreds of gates

43. Wednesday, October 07, 2015 42 WHY CPLD? In case of the 7400 IC, 4 circuits of 2 input NAND gate are housed. In case of 7404, 6 circuits of inverter are housed. In case of CPLD, it has wiring among the logic in the IC. So, the wiring on the printed board can be made little. the wiring on the printed board can be made little.

44. Wednesday, October 07, 2015 43 (II) COMPLEX PROGRAMMABLE LOGIC DEVICE (CPLD):: PROGRAMMABLE SWITCH MATRIX

45. Wednesday, October 07, 2015 44 Example CPLD Families ::  Altera MAX 7000 and MAX 9000 families  Atmel ATF and ATV families  Lattice ispLSI family  Lattice (Vantis) MACH family  Xilinx XC9500 family

46. Wednesday, October 07, 2015 45 CPLD EXAMPLE ::

47. Wednesday, October 07, 2015 46 (III) FIELD PROGRAMMABLE GATE ARRAY :: first introduced Xilinx in 1984. FPGA, first introduced by Xilinx in 1984. Itreprogrammable logic device It is a reprogrammable logic device that implements multilevel logic.

48. Wednesday, October 07, 2015 47 CLB IO FPGA ::  Configurable Logic Block (CLB)  Programmable Interconnect  IO Block

49. Elements of an FPGA Logic Element (LE). Interconnect. I/O pins. … LE interconnect IOB …

50. Wednesday, October 07, 2015 49 Configurable Logic Blocks:-

51. Wednesday, October 07, 2015 50 Programmable Interconnect::

52. Wednesday, October 07, 2015 51 Configurable I/O Blocks::

53. Wednesday, October 07, 2015 52 Example FPGA Families:: SSRAM based FPGA families AAltera FLEX family AAtmel AT6000 and AT40K families LLucent Technologies ORCA family XXilinx XC4000 and Virtex families AAnti-fuse based FPGA families AActel SX and MX families QQuicklogic pASIC family

54. Wednesday, October 07, 2015 53 Choosing Between CPLDs and FPGAs :: Choosing Between CPLDs and FPGAs ::

55. Wednesday, October 07, 2015 54 CPLD Vs. FPGA : :

56. Wednesday, October 07, 2015 55 THANK YOU