1. UT Oct. 2004 -- DeHon Sub-lithographic Semiconductor Computing Systems André DeHon andre@cs.caltech.edu In collaboration with Helia Naeimi, Michael Wilson, Charles Lieber, Patrick Lincoln, and John Savage

2. UT Oct. 2004 -- DeHon Approaching the Bottom In 1959, Feynman pointed out we had –“plenty of room at the bottom” Suggested: –wires ~ 10-100 atoms diameter –circuits ~ few thousands angstroms ~ few hundred nm

3. UT Oct. 2004 -- DeHon Approaching the Bottom Today we have 90nm Si processes –bottom is not so far away Si Atom –0.5nm lattice spacing –90nm ~ 180 atoms diameter wire

4. UT Oct. 2004 -- DeHon Exciting Advances in Science Beginning to be able to manipulate things at the “bottom” -- atomic scale engineering –designer/synthetic molecules –carbon nanotubes –silicon nanowires –self-assembled mono layers –designer DNA

5. UT Oct. 2004 -- DeHon Question Can we build interesting computing systems without lithographic patterning? Primary interest: below lithographic limits

6. UT Oct. 2004 -- DeHon Why do we care? Lithographic limitations –Already stressing PSM –…xrays, electron projection… Lithographic costs Source: Kahng/ITRS2001

7. UT Oct. 2004 -- DeHon Today’s Talk Bottom up tour: from Si atoms to Computing Nanowire –growth –devices –assembly –differentiation –coding Nanoscale memories from nanowires Logic: nanoPLAs Interconnected nanoPLAs Analysis

8. UT Oct. 2004 -- DeHon SiNW Growth Atomic structure determines feature size Self-same crystal structure constrains growth Catalyst defines/constrains structure

9. UT Oct. 2004 -- DeHon SiNW Growth

10. UT Oct. 2004 -- DeHon SiNW Growth

11. UT Oct. 2004 -- DeHon Building Blocks

12. UT Oct. 2004 -- DeHon Semiconducting Nanowires Few nm’s in diameter (e.g. 3nm) –Diameter controlled by seed catalyst Can be microns long Control electrical properties via doping –Materials in environment during growth –Control thresholds for conduction From: Cui…Lieber APL v78n15p2214

13. UT Oct. 2004 -- DeHon Radial Modulation Doping Can also control doping profile radially –To atomic precision –Using time Lauhon et. al. Nature 420 p57

14. UT Oct. 2004 -- DeHon Devices Diode and FET Junctions Doped nanowires give: Huang…Lieber Science 294 p1313 Cui…Lieber Science 291 p851

15. UT Oct. 2004 -- DeHon Langmuir-Blodgett (LB) transfer Can transfer tight-packed, aligned SiNWs onto surface –Maybe grow sacrificial outer radius, close pack, and etch away to control spacing + Transfer aligned NWs to patterned substrate Transfer second layer at right angle Whang, Nano Letters 2003 (to appear)

16. UT Oct. 2004 -- DeHon Homogeneous Crossbar Gives us homogeneous NW crossbar –Undifferentiated wires –All do the same thing

17. UT Oct. 2004 -- DeHon Control NW Dopant Can define a dopant profile along the length of a wire –Control lengths by timed growth –Change impurities present in the environment as a function of time Gudiksen et. al. Nature 415 p617 Björk et. al. Nanoletters 2 p87

18. UT Oct. 2004 -- DeHon Control NW Dopant Can define a dopant profile along the length of a wire –Control lengths by timed growth –Change impurities present in the environment as a function of time Get a SiNW banded with differentiated conduction/gate-able regions Gudskien et. al. Nature 415 p617 Björk et. al. Nanoletters 2 p87

19. UT Oct. 2004 -- DeHon Enables: Differentiated Wires Can engineer wires – Portions of wire always conduct) –Portions controllable

20. UT Oct. 2004 -- DeHon Coded Wires By selectively making bit-regions on wires either highly or lightly doped –Can give the wire an address

21. UT Oct. 2004 -- DeHon Unique Set of Codes If we can assemble a set of wires with unique codes –We have an address decoder

22. UT Oct. 2004 -- DeHon Unique Set of Codes If we can assemble a set of wires with unique codes –We have an address decoder Apply a code –k-hot code Unique code selects a single wire

23. UT Oct. 2004 -- DeHon Statistical Coding Unique Code set achievable with statistical assembly (random mixing) Consider: –Large code space (10 6 codes) –Large number of wires of each type (10 12 ) –Small array (10 wires) chosen at random Likelihood all 10 unique? –Very high! (99.995%) DeHon et. al. IEEE TNANO v2n3p165

24. UT Oct. 2004 -- DeHon Codespace: How Large? How large does code space really need to be? –Addressing N wires –With code space 100N 2 –Has over 99% probability of all wires being unique –For logarithmic decoder: Need a little over 2  bits of sparse code

25. UT Oct. 2004 -- DeHon Switches / Memories Molecular Switches Collier et. al. Science 289 p1172 Electrostatic Switches Ruekes et. al. Science 289 p04

26. UT Oct. 2004 -- DeHon Common Switchpoint Properties Fit in space of NW crossing Hysteretic I-V curves Set/reset with large differential voltage across crosspoint Operate at lower voltage

27. UT Oct. 2004 -- DeHon Memories

28. UT Oct. 2004 -- DeHon Basis for Sublithographic Memory

29. UT Oct. 2004 -- DeHon Precharge all lines low

30. UT Oct. 2004 -- DeHon Drive Column Read Address

31. UT Oct. 2004 -- DeHon Pulls Single Column Line High

32. UT Oct. 2004 -- DeHon On xpoint allow to pull Row lines to be pulled high Assume here: only the two points shown are “on”. i.e. column has 0 1 0 0 1 0

33. UT Oct. 2004 -- DeHon All Rows Disabled Read output not driven; sees 0

34. UT Oct. 2004 -- DeHon Select Read Row 1010 Read output now pulled high; sees 1

35. UT Oct. 2004 -- DeHon Select Read Row 1100 Read output not driven; sees 0

36. UT Oct. 2004 -- DeHon …on to Logic…

37. UT Oct. 2004 -- DeHon Diode Logic Arise directly from touching NW/NTs Passive logic Non-restoring Non-volatile Programmable crosspoints

38. UT Oct. 2004 -- DeHon Use to build Programmable OR-plane But.. –OR is not universal –Diode logic is non-restoring  no gain, cannot cascade

39. UT Oct. 2004 -- DeHon PMOS-like Restoring FET Logic Use FET connections to build restoring gates Static load –Like NMOS (PMOS) Maybe precharge

40. UT Oct. 2004 -- DeHon Operating Point: Make Restoring

41. UT Oct. 2004 -- DeHon Ideal vs. Stochastic Restore

42. UT Oct. 2004 -- DeHon Simple Nanowire-Based PLA NOR-NOR = AND-OR PLA Logic

43. UT Oct. 2004 -- DeHon Defect Tolerant All components (PLA, routing, memory) interchangeable; Have M-choose-N property Allows local programming around faults

44. UT Oct. 2004 -- DeHon Simple PLA Area 60 OR-term PLA –Useable 131 raw row wires –Defects –Misalign 171 raw inverting wires –Defects –Statistical population 60M sq. nm. –(2 planes) 90nm support lithography; 10nm nanowire pitch

45. UT Oct. 2004 -- DeHon Crosspoint Defects Crosspoint junctions may be nonprogrammable –E.g. HPs first 8x8 had 85% programmable crosspoints Tolerate by matching nanowire junction programmability with pterm needs Less than ~10% overhead for crosspoint defect rates up to 20% Naeimi/DeHon, FPT2004

46. UT Oct. 2004 -- DeHon Interconnected nanoPLAs

47. UT Oct. 2004 -- DeHon Tile into Arrays

48. UT Oct. 2004 -- DeHon Manhattan Routing

49. UT Oct. 2004 -- DeHon Manhattan Routing

50. UT Oct. 2004 -- DeHon Tile into Arrays

51. UT Oct. 2004 -- DeHon Complete Substrate for Computing Know NOR gates are universal Selective inversion Interconnect structure for arbitrary routing  Can compute any logic function Can combine with nanomemories

52. UT Oct. 2004 -- DeHon Interconnected nanoPLA Tile

53. UT Oct. 2004 -- DeHon Analysis

54. UT Oct. 2004 -- DeHon Ideal vs. Stochastic Restore

55. UT Oct. 2004 -- DeHon Various Area Models

56. UT Oct. 2004 -- DeHon Technology: Lithographic Support + Diode Pitch

57. UT Oct. 2004 -- DeHon Area Mapped Logic Take standard CAD/Benchmark designs –Toronto20 used for FPGA evaluation Map to PLAs Place and Route on arrays of various configurations Pick Best mapping to minimize Area

58. UT Oct. 2004 -- DeHon Mapped Logic Density (105/10/5)

59. UT Oct. 2004 -- DeHon Nanowire Lengths: 105/10/5/Ideal Restore/Pc=0.95

60. UT Oct. 2004 -- DeHon Cycle Delay: 105/10/5/Ideal Restore/Pc=0.95

61. UT Oct. 2004 -- DeHon Power Density (per GHz) Vdd=1V Active Power Precharge

62. UT Oct. 2004 -- DeHon Construction Review Seeding control NW diameter Timed growth controls doping profile along NW LB flow to assemble into arrays Timed etches to separate/expose features Assemble on lithographic scaffolding Stochastic construction of address coding allow micro  nanoscale addressing Differentiate at nanoscale via post-fabrication programming All compatible with conventional semiconductor processing –Key feature is decorated nanowires

63. UT Oct. 2004 -- DeHon Summary Can engineer designer structures at atomic scale Must build regular structure –Amenable to self-assembly Can differentiate –Stochastically –Post-fabrication programming Sufficient building blocks to define universal computing systems without lithography Reach or exceed extreme DSM lithography densities –With modest lithographic support

64. UT Oct. 2004 -- DeHon Additional Information