1. Synthesis Presented by: Ms. Sangeeta L. Mahaddalkar ME(Microelectronics) Sem II Subject: Subject:ASIC Design and FPGA

2. Topics Discussed  Introduction to Synthesis  Synthesis process  Synthesis Tools  Guidelines for coding  Synthesis examples

3. SYNTHESIS  Automatic method of converting a higher level of description of the design into an optimized gate level description given standard cell library (Technology library) and certain design constraints  Synthesis tools convert High Level descriptions (HDL Description) into gate level netlists

4. Gate level netlist synthesis Technology Library High Level Description Constraints Gate Level Netlist Synthesis Timing, Area, Testability, Power VHDL, Verilog Standard cell library – logic gates, macrocells

5. SYNTHESIS PROCESS VHDL RTL Description Unoptimized Boolean Description Optimized Boolean Description Gate Level Netlist Translate Optimize Map to Gates Created by user Created by synthesis tool

6. Synthesis Process …  Translation –Converting from RTL Description to boolean equivalent description –IF, CASE, LOOP, Conditional signal assignment statements, Selected signal assignment statements are converted to their boolean equivalent form.

7. Synthesis Process…  Boolean Optimization –convert an unoptimized boolean description into optimized boolean form –Quine-McCluskey Algorithm was used earlier –Presently Espresso heuristic logic minimizer is a standard tool for optimization – Logic optimization algorithms generally work either on the structural (SOP, factored form) or functional (BDD) representation of the circuit.  Mapping to Gates –Takes logically optimized boolean description created by optimization step and uses logical and timing information from technology library to build a netlist

8. SYNTHESIS TOOLS   Software tools for logic synthesis targeting ASICsASICs – –Design Compiler by Synopsys – –Encounter RTL Compiler by Cadence Design System – –BuildGates an older product by Cadence Design System – –BlastCreate by Magma Design Automation – –BooleDozer Logic synthesis tool by IBM   Software tools for logic synthesis targeting FPGAsFPGAs – –Encounter RTL Compiler by Cadence Design System – –Leonardo Spectrum and Precision (RTL/Physical) by Mentor Graphics – –Synplify (PRO / Premier) by Synplicity – –BlastFPGA by Magma Design Automation – –Quartus II integrated Synthesis by Altera – –XST (delivered within ISE) by Xilinx – –DesignCompiler Ultra and IC Compiler by Synopsys – –IspLever by Lattice Semiconductor

9. Synthesis from VHDL / VERILOG 1. Layout synthesis 2. Logic synthesis 3. RTL synthesis 4. High Level Synthesis 5. System Synthesis

10. Coding for Synthesis  VHDL and Verilog are hardware description languages and simulation languages that were not originally intended as inputs to synthesis.  Therefore, many hardware description and simulation constructs are not supported by synthesis tools.  VHDL and Verilog semantics are well defined for design simulation. The synthesis tools must adhere to these semantics to ensure that designs simulate the same way before and after synthesis.

11. Guidelines to be followed to create code that simulates the same way before and after synthesis. 1.Omit the Wait for Statement  eg. Wait for 20 ns; - VHDL construct  # 20 ns; - Verilog construct  This statement does not synthesize to a component.  This statement does not synthesize to a component. In order to describe a similar “wait-for-time effect” that can be synthesized, we need to describe it as an FSM state that self-loops until a counter (set or reset at an earlier state) reaches a count value that translates to the desired wait time needed (Count value decided based on the clock speed).

12. Guidelines contd … 2.Omit the...After clause or Delay Statement ...After XX ns statement in VHDL code.  Delay assignment in Verilog code. eg.  Q <=0 after 20 ns;- VHDL  assign #20 Q=0;- Verilog  These statements are usually ignored by the synthesis tool.

13. Guidelines contd … 3. Omit Initial Values  Do not assign signals and variables initial values because initial values are ignored by most synthesis tools.  Eg. do not use initialization statements like  signal sum : integer := 0; - VHDL  initial sum = 1’b0;- Verilog

14. Guidelines contd … 4. Order and Group Arithmetic Functions  The ordering and grouping of arithmetic functions can influence design performance. eg.ADD1 <= A1 + A2 + A3 + A4; -Statement 1 ADD1 <= (A1 + A2) + (A3 + A4); -Statement 2  The first statement cascades three adders in series.  The second statement creates two adders in parallel: A1 + A2 and A3 + A4. In the second statement, the two additions are evaluated in parallel and the results are combined with a third adder.  RTL simulation results are the same for both statements, however, the second statement results in a faster implementation

15. Guidelines contd … 5.Don’t Mix positive and negative edge triggered flipflops in a design It may introduce inverters and buffers in the clock tree. This can add clock skews in the circuit.

16. library IEEE; use IEEE.STD_LOGIC_1164.ALL; entity t12 is Port ( a,b,c,d,e : in std_logic; o : out std_logic); end t12; architecture Behavioral of t12 is signal temp:std_logic; begin process(a,b,c,d,e) begin temp<=a xor b; temp<=temp xor c; temp<=temp xor d; temp<=temp xor e; end process; o<=temp; end Behavioral; Wrong Hardware Inferred Logic Synthesis Examples

17. Examples… library IEEE; use IEEE.STD_LOGIC_1164.ALL; entity t12 is Port ( a,b,c,d,e : in std_logic; Port ( a,b,c,d,e : in std_logic; o : out std_logic); o : out std_logic); end t12; architecture Behavioral of t12 is begin begin process(a,b,c,d,e) process(a,b,c,d,e) variable temp:std_logic; begin begin temp:=a xor b; temp:=a xor b; temp:=temp xor c; temp:=temp xor c; temp:=temp xor d; temp:=temp xor d; temp:=temp xor e; temp:=temp xor e; o<=temp; o<=temp; end process; end process; end Behavioral; Correct Hardware Inferred

18. Combinational Logic Synthesis library IEEE; use IEEE.STD_LOGIC_1164.ALL; entity t12 is Port ( a,b,clk : in std_logic; Port ( a,b,clk : in std_logic; o : out std_logic); o : out std_logic); end t12; architecture combinational of t12 is Beginprocess(clk,a,b)Begin o<=a and b and clk; end process; end combinational; 2 Input AND gate with enable

19. Sequential Logic Synthesis library IEEE; use IEEE.STD_LOGIC_1164.ALL; entity t12 is Port ( a,b,clk : in std_logic; Port ( a,b,clk : in std_logic; o : out std_logic); o : out std_logic); end t12; architecture sequential of t12 is Beginprocess(clk,a,b)Begin if(clk'event and clk='1')then o<= a and b; o<= a and b; end if; end process; end sequential ; Note: Here we are assigning on edge of clk. Hence it infers a Flipflop

20. Latch inference library IEEE; use IEEE.STD_LOGIC_1164.ALL; entity t12 is Port ( a,b,clk : in std_logic; o : out std_logic); o : out std_logic); end t12; Architecture latch of t12 is begin beginprocess(clk,a,b)begin if(clk='1')then if(clk='1')then o<= a and b; o<= a and b; end if; end process; end latch; Note: Here we are assigning on level of clk. Hence it infers a latch

21. Mux Coding - Latch Inferred module mux(a,b,sel, o); input a,b,sel; input a,b,sel; output o; output o; reg o; reg o; always @(a or b or sel) always @(a or b or sel) begin begin case(sel) case(sel) 1'b0: o<=a; 1'b0: o<=a; endcase endcase end endendmodule Note: Here one of the inputs is not assigned to output. Hence Latch inferred

22. Mux Coding - Latch Inferred… module mux(a,b,sel, o); input a,b,sel; input a,b,sel; output o; output o; reg o; reg o; always @(a or b or sel) always @(a or b or sel) begin begin casex(sel) casex(sel) 1'b0: o<=a; 1'b1: o<=b; 1'b1: o<=b;endcaseendendmodule Note: casex statement used. Latch inferred

23. Correct Mux Inferred module mux(a,b,sel, o); input a,b,sel; input a,b,sel; output o; output o; reg o; reg o; always @(a or b or sel) always @(a or b or sel) begin begin case(sel) case(sel) 1'b0: o<=a; 1'b0: o<=a; 1'b1: o<=b; 1'b1: o<=b; default: o<=1’bx; default: o<=1’bx; endcase endcase end end endmodule endmodule

24. Regitered Decoder Synthesis module mux(clk,reset,data,q); input clk,reset; input clk,reset; input [1:0]data; input [1:0]data; output [3:0]q; output [3:0]q; reg [3:0] q; reg [3:0] q; wire [1:0] d; always @(posedge clk) if (reset) q <= 4'b0; if (reset) q <= 4'b0; else else case (data) case (data) 2'b00 : q <= 4'b0001; 2'b00 : q <= 4'b0001; 2'b01 : q <= 4'b0010; 2'b01 : q <= 4'b0010; 2'b10 : q <= 4'b0100; 2'b10 : q <= 4'b0100; 2'b11 : q <= 4'b1000; 2'b11 : q <= 4'b1000; default : q <= 4'b0000; default : q <= 4'b0000; endcase endcaseendmodule

25. References  VHDL – Programming By examples – Douglas L. Perry  en.wikipedia.org/wiki/Logic_synthesis  Application Specific IC’s – M.J. Smith