1. 1 of 19 09/09/2013 FE-I4B IBL wafer probing results FE-I4 testing meeting 09 September 2013 Marlon Barbero, David-Leon Pohl Introduction Cut definitions Results

2. 2 of 19 09/09/2013 Status: FE-I4Bs for IBL stavesICs/stave safety margin pessimistic yield estimation of 50% green ICs (=30) per Wafer Marlon Barbero, David-Leon Pohl 100% planar 25% 3D FE-I4 wafer

3. 3 of 19 09/09/2013 FE-I4B wafer probing requirements setup new PCB with new needle card automated voltage/current measurements, switches control DAQ software with FE-I4B capabilities Analysis software for automated data analysis maintaining: Changes/rework/cleaning of needle cards (hot needles, tip shape) Probe card fixes (floating needle at not EFUSE protected pad) Probe station PC reparation (virus, power supply broken) 5 power cuts FE-I4B wafer probing setup in Bonn Marlon Barbero, David-Leon Pohl

4. 4 of 19 09/09/2013 Cut scheme of WaferAnalysis Color definition, chip states suitable for IBL some defects (broken column, higher current…) analysis result needs attention and has to be judged manually not usable (crazy current) Each scan result has its own status! Blue is allowed here The final chip status is: green, yellow, red, NOT blue the worst result status defines the chip status Marlon Barbero, David-Leon Pohl Cuts are applied on > 18000 values per wafer

5. 5 of 19 09/09/2013 Cut scheme of WaferAnalysis Cuts on three levels: pixel, column and global IC cuts Marlon Barbero, David-Leon Pohl

6. 6 of 19 09/09/2013 Cut scheme of WaferAnalysis Global IC cuts example: analog current after power up > 150 mA > 9 mA Marlon Barbero, David-Leon Pohl > 150 mA > 9 mA< 0 mAelse cut order, values from cut file version 0.8

7. 7 of 19 09/09/2013 Pixel cuts Column cuts Global IC cuts Defines here: what is a analog scan failing pixel Defines here: How many pixel in one column have to fail the analog scan to let the DC fail Defines here for the analog scan result and the blue, red, yellow IC states: - how many pixels can fail in the analog test - how many columns can fail in the analog test And defines the total cuts AnalogHits!=200 AnalogFailPixel>20 AnalogFailPixel>26880 AnalogFailColumns>80 TotalFailPixel>108 TotalFailColumns!=0 AnalogFailColumns!=0 AnalogFailPixel>10000 else Cut scheme of WaferAnalysis Pix/col based cuts example: Analog Scan Total pix/col failing add to Marlon Barbero, David-Leon Pohl

8. 8 of 19 09/09/2013 Pixel cuts Cut scheme of WaferAnalysis Pixel based cuts example: Analog Scan AnalogHits!=200  466 analog failing pixels Analog failing pixels > 20  2 analog failing columns Total pix/col failing TotalFailPixel>108 TotalFailColumns!=0 AnalogFailColumns!=0 Marlon Barbero, David-Leon Pohl

9. 9 of 19 09/09/2013 FE-I4B wafer testing What is done at wafer level Chip calibrations Reference current tuning Pulser DAC transfer function Injection capacitance measurement 15-bit serial number burning Global chip tests Current consumption (in different chip states) Global register test Tunable/fixed V ref Service records Scan chain tests Injection delay scan of internal pulser Pixel array tests Pixel register test Digital test Analog test with different C inj Threshold scan … Can only be done at wafer level Marlon Barbero, David-Leon Pohl Aptasic tests IDDQ tests Scan chain tests Shmoo plots Current consumption

10. 10 of 19 09/09/2013David-Leon Pohl FE-I4B wafer testing results: reference current Used to deduce all biasing voltages, feed DACs Can be set only externally via PADs (4-bits) Design value of 2 µA can be reached with small error (< 25 nA)

11. 11 of 19 09/09/2013David-Leon Pohl FE-I4B wafer testing results: voltage references (input for LDOs) Issue : Absolute voltage measurements suffer from GND shift  measurements depend on the current drawn by the IC Resitance from needles, cables, chip, etc. Example band gap analog voltage: 763 mV / 108 mA total current 803 mV / 221 mA total current 826 mV / 371 mA total current Idea: Measure the voltages more than once for differend chip current states Extrapolate to total current = 0 for the „real“ voltage FE-I4B R ‚real‘ GND ‚real‘ voltage R V GND voltage BgAnCorr: 733 mV Band gap analog on SCC Band gap analog on chuck BgAnCorr: 704 mV Systematic error: O(30 mV) (4%)

12. 12 of 19 09/09/2013David-Leon Pohl FE-I4B wafer testing results: band gap voltage references Measured band gap voltages have also (exactly) 30 mV offset to the design values (600 mV / 750 mV) No precise measurement of reference voltage possible on wafer level no regulator powering (time constrains, powering not fixed)  regulator output votlage tuned on module level (572 ± 11) mV(719 ± 13) mV

13. 13 of 19 09/09/2013David-Leon Pohl FE-I4B wafer testing results: tunable voltage references 750 mV for VDDA = 1.5V often not reached  IBL has 1.4 V analog voltage (476 ± 31) mV(710 ± 30) mV (479 ± 30) mV (712 ± 30) mV

14. 14 of 19 09/09/2013David-Leon Pohl FE-I4B wafer testing results: calibration of internal charge injection circuit Injection capacitance: (6.1 ± 0.3) fF Simulated value: 5.7 fF (>10 % error) PlsrDAC slope (14.3 ± 160) mV/DAC PlsrDAC maximum < 1 V  IC yellow

15. 15 of 19 09/09/2013David-Leon Pohl FE-I4B wafer testing results: threshold and noise Injection capacitance: (6.1 ± 0.3) fF Simulated value: 5.7 fF Mean threshold > 2000 e (no tuning!) Noise ~ 120 e, often non gaussian noise distribution

16. 16 of 19 09/09/2013David-Leon Pohl FE-I4B wafer testing results: and much more Injection capacitance: (6.1 ± 0.3) fF Simulated value: 5.7 fF Digital/analog test with different Cin Scan chain errors Service record counters indicating errors != 0 Global/pixel register tests Latency counter test Injection delay test Cross talk test Pixel hit buffer test (all bits of all buffers) Hit Or test

17. 17 of 19 09/09/2013David-Leon Pohl FE-I4B wafer testing: main failures > 0.2% (=54/26880) pixels fail current consumption too high (> 350 mA aborts the run to extend needle’s life) PlsrDAC often (> 2%) disqualified FE

18. 18 of 19 09/09/2013David-Leon Pohl FE-I4B wafer testing: yield Final yield: 61.0% green (for IBL), 30.5% yellow, 8.5% red Yield of upper edge ICs bad  mask alignment

19. 19 of 19 09/09/2013 Summary and outlook Summary: All IBL wafers = 2580 FE-I4Bs fully probed Yield = 61.0% (for IBL), 30.5%, 8.5% ~ 1% yield loss due to mask alignement tuneable voltage references slightly too low for analog voltage = 1.5 V Marlon Barbero, David-Leon Pohl

20. 20 of 19 09/09/2013 Appendix… David-Leon Pohl, Marlon Barbero

21. 21 of 19 09/09/2013 The side story with Aptasic Marlon Barbero, David-Leon Pohl -Idea: Provide additional tests that USBpix is (currently) not capable of (IDDQ, Shmoo plots) -Also tested (current consumption, scan chain) -Problems: -6 times wrong labeling of wafers, 2 wafers with own naming convention -Often current failure measured (often negative currents!) -2 ICs often not tested -Decision: to not proceed with Aptasic (only 21 wafers tested by A.) Scan chain test IDDQ difference

22. 22 of 19 09/09/2013 The side story with Aptasic II Marlon Barbero, David-Leon Pohl Bonn: Wafer VBAXYHH Aptasic: Wafer ID W01 (??) Powering failing chips I(VDDA2) AP/CFG 133/389 mA I(VDDD2) AP/CFG 231/241 mA I(VDDD2) AP/CFG 218/229 mA I(VDDA2) AP/CFG 1/147 mA I(VDDD2) AP/CFG 103/138 mA I(VDDD2) AP 455 mA -Aptasic wafer map is the mirrored Bonn map (y-axis) -Propability: German-Lottery:

23. 23 of 19 09/09/2013 The WaferAnalysis program Wafer Summary Chip Summary Setting file Cut configuration file STControl data WaferAnalysis (analyzes > 18000 values per wafer) two files per chip (scan data/cfg) map distribution scan plots Project file Project file - <WaferStatistic RedChips="2" database XML file input/output Marlon Barbero, David-Leon Pohl

24. 24 of 19 09/09/2013 Which fraction of failing pixels to accept? Outdated plot: Only first and better 15 wafers taken into acount Pixel register fails are mistakenly not taken into account 1 column 1 DC Marlon Barbero, David-Leon Pohl 4,2% less failing ICs / 1% more failing pixel allowed

25. 25 of 19 09/09/2013 -Keithley 2410 for Iref curr. meas. -Keithley 2410 for Icap curr. meas. -Keithley 2001 + 2000 scanner card for -Voltage measurement: -VrefOutDig -VrefOutAn -BgVrefDg -BgVreAn -PlsrDac -Switch on/off Iref switch via digital I/O -National Instrument USB-GPIB-B adapter -TTi QL355TP power supply for regulators and multi-IO board + one TTi for cap measure? -4-channel single throw 3.3V switch to control Iref pads via multi-IO board -In test setup: external Dual SPDT analog switch (switch is integrated on needle card) Wafer testing setup: proof of concept on the desk Marlon Barbero, David-Leon Pohl

26. 26 of 19 09/09/2013 From FE-I4A to FE-I4B wafer probing I Many new things to do at wafer level (written in red) Scans: Current consumption after power up and after configuration Scan chain tests for 3 peripheral digital logic blocks (DOB, CMD, ECL) Analog/digital scan Latency counter test (in each PDR) Global and pixel register tests Analog/digital band gap references, analog/digital Vrefs from Iref Buffer ToT test (for each pixel) Hit Or test threshold scan analog/digital scan Clow/Chigh analog scan Crosstalk scan Current @ high trigger frequency test Injection delay scan Service records Chip Calibration on wafer level: Reference current tuning Pulser DAC transfer function Injection capacitance measurement 15-bit serial number burning: chip number (6-bit), wafer number (9-bit) Marlon Barbero, David-Leon Pohl