1. VLSI ‘Physics, Characterization and Technology’ Activities at IIT Bombay Microelectronics Group, Department of Electrical Engineering 2002 http://www.ee.iitb.ac.in/~microel Prof. V. Ramgopal Rao

2. Overview Main thrust in silicon CMOS devices Extensive work on physics, characterization and technology aspects of CMOS and other compound semiconductors Developed novel characterization techniques for CMOS which are currently used by industry Projects of national importance Large number of projects from multinational industries Extensive consultation work for industry

3. Faculty - CMOS Physics, Technology and Characterization A. N. Chandorkar S. Duttagupta R. Lal S. Mahapatra V. Ramgopal Rao D. K. Sharma J. Vasi R.O.Dusane (ME&MS)

4. Areas of R & D Technology for CMOS and novel process development (down to 50 nm technology node) Development of novel electrical characterization techniques for Bulk and SOI MOSFETs Solar Cells on Flexible Substrates Sensors Silicon CMOS physics (SOI and Bulk) Bio-MEMS Emerging Areas  Interaction between VLSI technology and design  Strong Interdisciplinary activity

5. Technology CMOS Technologies for Special Applications (for radiation and other hazardous environments) Novel Unit Process Development/Optimization Full process integration for Novel structures In-house development of process equipment Solar Cells on Flexible Substrates Sensors Bio-MEMS (Please see Prof. R.Lal’s presentation)

6. Facilities Class 1000 Clean Room with a 5  m CMOS Facility Excellent characterization facility SEM; photoluminescence VLSI design workstations Simulation workstations Various TCAD tools and Design Software Intel Microelectronics Lab TCS VLSI Design Lab

7. Fabrication Facilities – IIT Bombay

8. Fabrication Laboratory Set-up in late 1980’s Full CMOS 2” wafer process facility worth over 5 crores One of its kind in an academic institution All equipment in working condition Several oxidation/diffusion furnaces Low pressure and atmospheric pressure CVD/Hot-Wire CVD furnaces Plasma Implantation system Mask aligner and photolithography Several vacuum evaporation systems Plasma processing systems Rapid Thermal Processing System Class 100 clean benches Fabrication monitoring equipment like SEM, ellipsometer, surface profiling, 4-probe, etc. RTP System

9. A Novel CMOS Process Integration for Sub 50 nm Technologies …..1 Full CMOS process integration with : Hot-Wire CVD (HWCVD) Silicon Nitride as gate dielectric In-situ doped low temperature (<250 o C) Polysilicon deposited by HWCVD as the gate material Plasma Implantation for Shallow Source/Drain regions Gate length defined by Reactive-Ion Etching T-gate structure to reduce the gate resistance

10. Process Flow …..2 We have already made the first devices, and further process optimization is currently underway.

11. Solar Cells on Flexible Substrates The defect density of a-Si:H is minimum (~10 15 cm -3 ) at a growth temperature of 200 - 250 ºC. Substrate Material Requirement:  Stable at 200 - 250 ºC.  Undeformed Impurity-free Plastics (Polyimide) Stainless Steel foil

12. Lightweight- ideal for millitary and space applications Lightweight- ideal for millitary and space applications Roll-to-roll process allows for ease of integration – power everywhere! Roll-to-roll process allows for ease of integration – power everywhere! Potential low cost technologies on the horizon-organic solar cells Potential low cost technologies on the horizon-organic solar cells Application of Flex Solar Cells

13. Flexible Solar Cells : Device structure Cell efficiency,  = V oc × J sc × FF P in i- a-Si:H Textured TCO ZnO p- a- SiC:H n- a-Si:H 30% T Ag Glass / TCO / p / i / n / Ag SS / ZnO / p / i / n /Ag Opaque (SS/Kapton)Glass V oc  Doped layers J sc  i-layer defect density  Light trapping FF  i-layer defect density  Interfaces

14. Rigid (TCO/Glass) vs. Flex (SS) J-V Properties of a-Si:H films (p, i, and n) were optimized for solar cells deposited on TCO/glass.  ~ 8%  ~ 2.5% Opaque (SSfoil/Kapton) p i n Glass p i n

15. Future Directions – Flexible Solar Cells Develop a low temp technique to get texturing on flexible substrates Multijunction a-Si solar cells to reduce instability Explore alternatives: microcrystalline Si, Organic cells High throughput roll-to-roll deposition process critical for commercialization

16. Sensors …1 Objective  Sensor for heavy metals candidates: Mercury, Lead broad range of concentrations chemical speciation field portable for in situ measurement

17. Sensors …2 environmental assessment contaminant and remediation monitoring “smart” waste site development Electrochemical Sensors Polythiophene based sensors

18. First Demonstration of ……….. Sub 100 nm Channel Length Lateral Asymmetric Channel (LAC) n-and p-MOSFETs on Bulk and SOI Substrates (in collaboration with University of California, Los Angeles) Planar Doped Barrier vertical MOSFETs down to 60 nm channel lengths and demonstration of velocity overshoot effects due to the delta channel doping (in collaboration with the Universitaet der Bundeswehr, Munich, Germany) In-situ Doped Polysilicon and Gate quality Nitride Depositions for CMOS Technologies using a novel Hot-wire CVD process High Performance Sub 100 nm MNSFETs using Jet-Vapor-Deposited Nitride as a Gate Insulator (in collaboration with Prof. T.P.Ma, Yale University and Prof. J.C.S.Woo, UCLA)

19. CMOS Characterization Extensive experimental work on sub-quarter micron Lateral Asymmetric Channel MOSFETs for Mixed Signal Applications CMOS Reliability Characterization for Digital and Analog Applications Reliability Characterization for Flash Memories Characterization of Vertical MOSFETs down to 60 nm Channel Lengths Novel Techniques for Plasma Damage Characterization in CMOS Devices New electrical techniques for Bulk and SOI MOSFET interface characterization

20. Facilities - Characterization Shielded probe stations with thermochuck (-60 o C to +150 o C) SEM with Electron-beam induced currents (EBIC) and voltage contrast attachments Large number of electrometers, Source-Measure-Units, Pulse Generators, Capacitance meters, bridges and plotters, signal analyzers etc. Photoluminescence setup High-, low- and combined high-low frequency C-V measurements High-field stressing of MOS and bipolar devices Avalanche injection measurements Bias-temperature and triangular voltage sweep (TVS) measurements DLTS I-V measurements of MOS and bipolar devices Charge pumping measurements, including defect profiling Hot-carrier measurements Gate transfer and delay characteristics Complete AC/DC Characterization facility for Non-volatile memories

21. Bulk and SOI MOSFETs Mixed Signal CMOS Device Optimization Charge Pumping Techniques Floating Body Effects in SOI Flicker Noise Measurements Plasma Process Induced Damage Atomic Force/Scanning Tunneling Microscope studies for defects Channel and Source/Drain Engineering for CMOS Hot-carrier Effects in CMOS and Flash Memories Gate Oxide Characterization and Reliability analysis Low-Temperature oxides Novel CMOS Device Structures Radiation Effects Molecular Electronics Extensive Characterization work related to …

22. Silicon CMOS physics CMOS Device Degradation Alleviating the Floating Body Effects in SOI MOSFETs Channel Engineering for Sub 100 nm MOSFET Optimization Velocity Overshoot Effects Short-Channel Effects Ultra-thin oxide Characterization Defect generation in ultra-thin Silicon oxides/nitrides Radiation effects, hot-carrier effects, high-field stressing, oxide breakdown, and ESD related issues in MOSFETs Fringing field effects in high-K gate dielectrics Quantum effects in ultra-short channel MOSFETs DNA Conduction Solar Cells Sensors

23. Emerging Areas – Molecular Electronics

24. Molecular Electronics at IIT Bombay (Collaborators: Prof. Soumyo Mukherji, Bio-medical Engg. and Prof. Ravikanth, Chemistry Dept., IIT Bombay) Electronic conduction in DNA studied by: Electron transfer rate reactions Direct electronic conduction Attach specific molecular devices to specific portions on a DNA array using a variety of linker porphyrins (Synthesis done. Electrical characterization underway) Nanoelectrode Fabrication

25. Sponsored Projects Projects of National Importance (Space, Defense) Projects cover all areas of Microelectronics & VLSI Projects from major government agencies, and leading Indian & international companies

26. Some Ongoing Projects: Physics & Technology Radiation Hard Technology for Space Applicaions (DOE) Microfabricated silicon sensors (MHRD) Sub 100 nm CMOS technology Development (MHRD) Silicon sensors for electroporation (Praman Technology) Characterization of SiGe HBTs (DST) Characterization of vertical MOS transistors (Siemens)

27. Some Ongoing Projects: Modeling & Simulation Development of a hot-carrier simulator (Motorola) Modeling of power semiconductor devices (GE) RF MOSFET Models (IME, Singapore) Oxide scaling effects on design issues (Intel)

28. Some Ongoing Projects: VLSI Design & CAD Tools Interconnect capacitance extraction by Monte Carlo (Intel) Interconnect parasitics extraction (SAS) High-speed comparator design (TII) Design issues with high-k dielectrics (Intel) VLSI Design training (MIT, TCS)

29. Industry Collaborations Projects with Indian industry: BEL, ITI, SAS, TI, Cypress, ControlNet, SCL etc Projects with international industry: Intel, Motorola, GE, Siemens, National, NTT, Sun Industry sponsorship of students Continuing Education Programs for industry

30. University Collaborations Collaborations with other IITs, Universities of Bombay, Pune Collaborations with International universities like UCLA, UCSB, Yale University (USA) Hong Kong University of Sc. & Tech. (HK) Delft University (The Netherlands) University of Bundeswehr (Germany) Griffith University (Australia) NUS, IME, NTU, IHPC (Singapore)

31. Publications Over 30 publications every year in major journals and conferences Over 40 technical reports in last 10 years Cover all areas of interest Details at www.ee.iitb.ernet.in/~microel/

32. Conclusions Most active Microelectronics & VLSI group in India Excellent research/fabrication facilities Projects of national importance Projects from Indian & international industry Major teaching programs at all levels