1. 1/1/ / faculty of Electrical Engineering eindhoven university of technology 5Z008:Microprocessor design Design steps

2. 1/1/ / faculty of Electrical Engineering eindhoven university of technology Agenda for the coming hours How to design a microprocessor –Step-by-step from ISA to hardware architecture –No processor the same: ‘architecture styles’ Additional info on ‘IDaSS’ –Memories –Timing –Hints & tips

3. 1/1/ / faculty of Electrical Engineering eindhoven university of technology OK, so what was an ‘ISA’ again? A ‘user’ oriented processor description Information needed to write programs –Where to store data, instructions and control info ‘Memory spaces’, registers & ‘flags’: number of words and bits, addressing, overlap and usage –Interactions with the ‘outside world’ Accessing I/O hardware, using interrupts –The actual instruction-set –Limitations and ‘side-effects’ of instructions Prefer none, but these may pop up in the hardware design…

4. 1/1/ / faculty of Electrical Engineering eindhoven university of technology The target: operational ‘hardware’ A description of the processor ‘architecture’ – ‘Visible’ parts of the ISA should be present Storage in RAM/ROM/registers/flags Basic operations in (combinatorial) logic circuits Interfaces with the outside world – Additional components to get this operational Communication channels between ISA components Extra registers/memories for temporary storage Instruction decoding & (sequential) control Find a balance between complexity & speed !

5. 1/1/ / faculty of Electrical Engineering eindhoven university of technology Steps in designing a processor (1) 0:Find the operational targets of the machine –Market research: let the customers decide –Functional requirements of ‘System On a Chip’ parts 1:Design an ISA (lots of cycles in here!) 1.1:Define ‘visible’ memory spaces, registers, flags and interfaces 1.2:Define ‘abstract’ instructions as operations using elements defined in step 1.1 1.3:Assign bit patterns to ‘abstract’ instructions

6. 1/1/ / faculty of Electrical Engineering eindhoven university of technology Steps in designing a processor (2) 2:Design the hardware architecture 2.1:Create the storage- and operational parts defined in the ISA 2.2:Add registers/memories for temporary storage (not in ISA!) 2.3:Connect everything so that all sub- operations can be executed 2.4:Design a control structure which schedules and controls all sub-operations This is the theory…

7. 1/1/ / faculty of Electrical Engineering eindhoven university of technology Step 1: analyse the ISA - storage Memory spaces –‘Real memory’ (RAM, ROM) or something else (‘SFR’s) –How can it be addressed (is there overlap ?) Indication for the logic needed for calculating addresses –Address decoding needed for more ‘things’ in one space Address-dependent handling to be done in control structure ! Registers (not mapped in memory acc. to ISA) –More than one with identical usage: ‘register file’ RAM ? Pack flag bits together in registers –Attach to logic which controls them (also for read/write)

8. 1/1/ / faculty of Electrical Engineering eindhoven university of technology Step 2: analyse the ISA - basic operations Chop instructions into basic steps –For instance with PUSH & CALL: ‘SP  SP + 1’ –Different bit-widths = different basic operations –Flag changes are basic operations too –Address calculations and read/write actions: ditto For speed: which basic op’s can run parallel ? –If never parallel: combining can save hardware Group basic operations by ‘place of execution’ –In ALU, ‘address generator’ or attached to registers For now only! Forms basis for the IDaSS ‘operators’

9. 1/1/ / faculty of Electrical Engineering eindhoven university of technology Step 3: add non-ISA registers Pretty standard: instruction register(s) –Retain first fetched part for decoding –May store remaining parts in separate registers Extra registers to improve timing –With slow memories at address, in- and/or outputs After choosing an ‘architecture-style’: Extra registers which are standard for this style –For instance a ‘TEMP’ register for a 2-bus architecture One register may serve more than one purpose !

10. 1/1/ / faculty of Electrical Engineering eindhoven university of technology Step 4: sketch a preliminary data- path Must have chosen an architecture-style to do this ! Connect all elements together –All basic operations must be possible –If necessary in more than one clock (extra registers !) –Try to adhere to grouping of basic op’s from step 2 Check these sketches before starting with IDaSS –Around registers: mux-operators & separate TS- buffers –Expensive operations in separate operators (for instance re-use the ‘+’ within an ALU) –Sub-parts in sub-schematics for better overview

11. 1/1/ / faculty of Electrical Engineering eindhoven university of technology Step 5: add the control machinery In general a single state controller (FSM) –Fetching the first part of an instruction always the same –Afterwards, handling depends upon actual instruction Split the work within the group, check eachother’s work ! Complete the data path during this step –Fill in the functions within ‘operator’ blocks Needs ‘version management’: distribute and integrate changes ! ‘Control inputs’ for local control without states –For instance for address decoding outside the processor

12. 1/1/ / faculty of Electrical Engineering eindhoven university of technology This is a group assignment… Analysis of ISA (steps 1 & 2): small groups –Check eachother’s results and unify Building a data path (steps 3 & 4): full team –Group discussion to obtain a rough sketch –Split work in small groups to enter parts in IDaSS After firm choices regarding the interfaces ! Creating control machinery (step 5): small groups –Split the instruction set (unary/binary/flow control) Perform cross-checking and appoint version manager !

13. 1/1/ / faculty of Electrical Engineering eindhoven university of technology ‘Architecture-styles’ Many ways to build a processor Strike a balance between complexity & speed –In principle: speed requires complexity Obtain speed by doing things in parallel –Complexity is expensive (parts and design time) –Too complex: clock speed will collapse ! Standard methods have arisen over time –Recognisable ‘architecture-styles’ –Sometimes mixtures for parts of the data path

14. 1/1/ / faculty of Electrical Engineering eindhoven university of technology ‘N-bus’ architectures (mostly N = 1..3) This simple data path is a 2-bus system ALU MAR MDR PC IR ACCU HULP A B- bus C- bus Data memory Program memory B A- bus More buses not always faster Fewer buses not always cheaper Partial-data paths for different bit-widths (f.i. data/addresses) With an extra ‘A-bus’ is a 3-bus system IDaSS example up8048n.des is a 1- bus systeem Do NOT tie everything to all buses !

15. 1/1/ / faculty of Electrical Engineering eindhoven university of technology ‘Destination-multiplexer’ systems N-bus systems use (a lot) TS-buffers –Slow and sometimes not allowed within a chip –Solution: replace TS-buffers and bus with multiplexer –Is not a functional change of the architecture ! A ‘destination-mux’ system takes this further Inputs of building blocks are connected with multiplexers to their possible sources –In IDaSS: operator blocks (can perform local op’s) –Can do more things in parallel: gives a faster processor ! But is easy to loose overview…

16. 1/1/ / faculty of Electrical Engineering eindhoven university of technology stage 3 Execute stage 2 Decode stage 1 Fetch ‘Pipeline’ architectures Split the handling of instructions in independent stages and execute the stages in parallel + 1 ALU Program memory PC Data registers s1s2 I1 S1 S2 I2 D I3 stage 4 Write d No central control… One clock per instruction: very fast ! But this is extremely simplified ! See pipeline.des for a real example For advanced designers!