1. ECEN 248: INTRODUCTION TO DIGITAL DESIGN
Lecture Set A
Dr. S.G.Choi
Dept. of Electrical and Computer Engineering 1

2. Instructor: Office 333G WERC Office Hours MWF 10-11 AM
Lab Page: 2

3. Required textbook:
Required Textbook: "Fundamentals of Digital Logic Design" by Brown and Vranesic. VERILOG VERSION
Supplemental texts: "Digital Design: Principles and Practices" by John Wakerly. "Contemporary Logic Design" by Randy Katz. 3

4. Course info Mailing list: Course website
s will be sent periodically to neo accounts
Announcements:
Lecture cancellations
Deadline extension
Updates, etc.
Course website
All slides, labs, assignments, etc. 4

5. Grading Policy: Assignments and Labs 25% 3 Hour Exams No Final Exam
20% for 1st exam
25% for 2nd
30% for 3rd
No Final Exam
Quizzes:
Each quiz 1% of the final
Taken into account only if it improves the final grade
Can improve the grade, but no extra points
Final grading may or may not be curved up 5

6. Quizzes: 3-6 quizzes Multiple choice questions 10-15 minutes
Each quiz 1% of the final
No quiz makeups 6

7. Grading scale
A standard grading scale will be utilized. The tentative grading scale for the course is: 
A       %
B         80-89%
C        70-79%
D         60-69%
F        Below 59% 7

8. Course Goals Study methods for
Representation, manipulation, and optimization for both combinatorial and sequential logic
Solving digital design problems
Study HDL description language (verilog) 8

9. Topics Number bases Logic gates and Boolean Algebra
Gate –label minimization
Combinational Logic
Sequential logic (Latches, Flip-flops, Registers, and Counters)
Memory and Programmable Logic
HDL language (Verilog) 9