1. 9/16/04UCB EECS150 D. Culler Fa04 1 EECS 150 - Components and Design Techniques for Digital Systems Lec 06 – Minimizing Boolean Logic 9/16-04 David Culler Electrical Engineering and Computer Sciences University of California, Berkeley http://www.eecs.berkeley.edu/~culler http://www-inst.eecs.berkeley.edu/~cs150

2. 9/16/04UCB EECS150 D. Culler Fa04 2 Review Combinational logic Truth Tables vs Boolean Expressions vs Gates Minimal Operators –And / Or / Not, NAND, NOR New Friends –XOR, EQ, Full Adder Boolean Algebra –+, *, ~, assoc, comm, distr., …. Manipulating Expressions and Circuits –Proofs: Term rewriting & Exhaustive Enumeration –Simplifications –De Morgan’s Law –Duality Canonical and minimal forms –Sum of products –Product of sums

3. 9/16/04UCB EECS150 D. Culler Fa04 3 Review: Relationship Among Representations *Theorem: Any Boolean function that can be expressed as a truth table can be written as an expression in Boolean Algebra using AND, OR, NOT. How do we convert from one to the other? Optimizations?

4. 9/16/04UCB EECS150 D. Culler Fa04 4 Review: Canonical Forms Standard form for a Boolean expression - unique algebraic expression directly from a true table (TT) description. Two Types: *Sum of Products (SOP) *Product of Sums (POS) Sum of Products (disjunctive normal form, minterm expansion). Example: mintermsa b c f f’ a’b’c’0 0 0 0 1 a’b’c0 0 1 0 1 a’bc’0 1 0 0 1 a’bc0 1 1 1 0 ab’c’1 0 0 1 0 ab’c1 0 1 1 0 abc’1 1 0 1 0 abc1 1 1 1 0 One product (and) term for each 1 in f: f = a’bc + ab’c’ + ab’c +abc’ +abc f’ = a’b’c’ + a’b’c + a’bc’

5. 9/16/04UCB EECS150 D. Culler Fa04 5 Review: Sum of Products (cont.) Canonical Forms are usually not minimal: Our Example: f = a’bc + ab’c’ + ab’c + abc’ +abc (xy’ + xy = x) = a’bc + ab’ + ab = a’bc + a(x’y + x = y + x) = a + bc f’ = a’b’c’ + a’b’c + a’bc’ = a’b’ + a’bc’ = a’ ( b’ + bc’ ) = a’ ( b’ + c’ ) = a’b’ + a’c’

6. 9/16/04UCB EECS150 D. Culler Fa04 6 Review: Canonical Forms Product of Sums (conjunctive normal form, maxterm expansion). Example: maxtermsa b c f f’ a+b+c0 0 0 0 1 a+b+c’0 0 1 0 1 a+b’+c0 1 0 0 1 a+b’+c’0 1 1 1 0 a’+b+c1 0 0 1 0 a’+b+c’1 0 1 1 0 a’+b’+c1 1 0 1 0 a’+b’+c’1 1 1 1 0 Mapping from SOP to POS (or POS to SOP): Derive truth table then proceed. One sum (or) term for each 0 in f: f = (a+b+c)(a+b+c’)(a+b’+c) f’ = (a+b’+c’)(a’+b+c)(a’+b+c’) (a’+b’+c)(a+b+c’)

7. 9/16/04UCB EECS150 D. Culler Fa04 7 ABCDWX YZ 00000001 00010010 00100011 00110100 01000101 01010110 01100111 01111000 10001001 10010000 1010XXXX 1011XXXX 1100XXXX 1101XXXX 1110XXXX 1111XXXX off-set of W these inputs patterns should never be encountered in practice – "don't care" about associated output values, can be exploited in minimization Incompletely specified functions Example: binary coded decimal increment by 1 –BCD digits encode decimal digits 0 – 9 in bit patterns 0000 – 1001 don't care (DC) set of W on-set of W

8. 9/16/04UCB EECS150 D. Culler Fa04 8 Outline Review De Morgan’s to transform SofP into simple 2-level forms Uniting Law to reduce SofP N-cube perspective Announcements Karnaugh Maps Examples Reduction Algorithm

9. 9/16/04UCB EECS150 D. Culler Fa04 9 Putting DeMorgan’s to work DeMorgan’s Law: (a + b)’ = a’ b’ (a b)’ = a’ + b’ a + b = (a’ b’)’ (a b) = (a’ + b’)’ push bubbles or introduce in pairs or remove pairs. == ==

10. 9/16/04UCB EECS150 D. Culler Fa04 10 Transformation to Simple Gates Sum of Products Involution: x = (x’)’ = De Morgans

11. 9/16/04UCB EECS150 D. Culler Fa04 11 Implementations of Two-level Logic Sum-of-products –AND gates to form product terms (minterms) –OR gate to form sum Product-of-sums –OR gates to form sum terms (maxterms) –AND gates to form product

12. 9/16/04UCB EECS150 D. Culler Fa04 12 Two-level Logic using NAND Gates Replace minterm AND gates with NAND gates Place compensating inversion at inputs of OR gate

13. 9/16/04UCB EECS150 D. Culler Fa04 13 Two-level Logic using NAND Gates (cont’d) OR gate with inverted inputs is a NAND gate –de Morgan's:A' + B' = (A B)' Two-level NAND-NAND network –Inverted inputs are not counted –In a typical circuit, inversion is done once and signal distributed

14. 9/16/04UCB EECS150 D. Culler Fa04 14 Two-level Logic using NOR Gates Replace maxterm OR gates with NOR gates Place compensating inversion at inputs of AND gate

15. 9/16/04UCB EECS150 D. Culler Fa04 15 Two-level Logic using NOR Gates (cont’d) AND gate with inverted inputs is a NOR gate –de Morgan's:A' B' = (A + B)' Two-level NOR-NOR network –Inverted inputs are not counted –In a typical circuit, inversion is done once and signal distributed

16. 9/16/04UCB EECS150 D. Culler Fa04 16 ABF001010101110ABF001010101110 B has the same value in both on-set rows – B remains A has a different value in the two rows – A is eliminated F = A'B'+AB' = (A'+A)B' = B' The Uniting Theorem Key tool to simplification: A (B' + B) = A Essence of simplification of two-level logic –Find two element subsets of the ON-set where only one variable changes its value – this single varying variable can be eliminated and a single product term used to represent both elements

17. 9/16/04UCB EECS150 D. Culler Fa04 17 1-cube X 01 Boolean cubes Visual technique for identifying when the uniting theorem can be applied n input variables = n-dimensional "cube“ Neighbors “address” differs by one bit flip 2-cube X Y 11 00 01 10 3-cube X Y Z 000 111 101 4-cube W X Y Z 0000 1111 1000 0111

18. 9/16/04UCB EECS150 D. Culler Fa04 18 ABF001010101110ABF001010101110 ON-set = solid nodes OFF-set = empty nodes DC-set =  'd nodes two faces of size 0 (nodes) combine into a face of size 1(line) A varies within face, B does not this face represents the literal B' Mapping truth tables onto Boolean cubes Uniting theorem combines two "faces" of a cube into a larger "face" Example: A B 11 00 01 10 F

19. 9/16/04UCB EECS150 D. Culler Fa04 19 ABCinCout 0000 0010 0100 0111 1000 1011 1101 1111 Cout = BCin+AB+ACin A(B+B')Cin the on-set is completely covered by the combination (OR) of the subcubes of lower dimensionality - note that “111” is covered three times Three variable example Binary full-adder carry-out logic A B C 000 111 101 (A'+A)BCin AB(Cin'+Cin)

20. 9/16/04UCB EECS150 D. Culler Fa04 20 F(A,B,C) =  m(4,5,6,7) on-set forms a square i.e., a cube of dimension 2 represents an expression in one variable i.e., 3 dimensions – 2 dimensions A is asserted (true) and unchanged B and C vary This subcube represents the literal A Higher dimensional cubes Sub-cubes of higher dimension than 2 A B C 000 111 101 100 001 010 011 110

21. 9/16/04UCB EECS150 D. Culler Fa04 21 m-dimensional cubes in a n- dimensional Boolean space In a 3-cube (three variables): –0-cube, i.e., a single node, yields a term in 3 literals –1-cube, i.e., a line of two nodes, yields a term in 2 literals –2-cube, i.e., a plane of four nodes, yields a term in 1 literal –3-cube, i.e., a cube of eight nodes, yields a constant term "1" In general, –m-subcube within an n-cube (m < n) yields a term with n – m literals

22. 9/16/04UCB EECS150 D. Culler Fa04 22 Announcements Homework 2 due Friday Reading: 2.5-2.8 (rest of ch 2) Homework 3 posted

23. 9/16/04UCB EECS150 D. Culler Fa04 23 ABF001010101110ABF001010101110 Karnaugh maps Flat map of Boolean cube –Wrap–around at edges –Hard to draw and visualize for more than 4 dimensions –Virtually impossible for more than 6 dimensions Alternative to truth-tables to help visualize adjacencies –Guide to applying the uniting theorem –On-set elements with only one variable changing value are adjacent unlike the situation in a linear truth-table 02130213 01 A B 0 1 1 00 1

24. 9/16/04UCB EECS150 D. Culler Fa04 24 Karnaugh maps (cont’d) Numbering scheme based on Gray–code –e.g., 00, 01, 11, 10 –2 n values of n bits where each differs from next by one bit flip »Hamiltonian circuit through n-cube –Only a single bit changes in code for adjacent map cells 02130213 0001 AB C 0 1 64756475 1110 C B A 02130213 64756475 C B A 04150415 128 139 D A 37263726 1511 1410 C B 13 = 1101= ABC’D

25. 9/16/04UCB EECS150 D. Culler Fa04 25 Adjacencies in Karnaugh maps Wrap from first to last column Wrap top row to bottom row 000010 001011 110100 111101 C B A A B C 000 111 101 100 001 010 011 110

26. 9/16/04UCB EECS150 D. Culler Fa04 26 obtain the complement of the function by covering 0s with subcubes Karnaugh map examples F = Cout = f(A,B,C) =  m(0,4,6,7) 0 00010001 101110111 Cin B A 10 B A 100010000 011101111 C B A B’ AB AC + ACin+ BCin + B’C’ + AB’

27. 9/16/04UCB EECS150 D. Culler Fa04 27 F(A,B,C) =  m(0,4,5,7) F'(A,B,C) =  m(1,2,3,6) F' simply replace 1's with 0's and vice versa G(A,B,C) = More Karnaugh map examples 0011 C B A 100010000 011101111 C B A 011101111 100010000 C B A A = AC + B’C’ = BC’ + A’C

28. 9/16/04UCB EECS150 D. Culler Fa04 28 find the smallest number of the largest possible subcubes to cover the ON-set (fewer terms with fewer inputs per term) K-map: 4-variable interactive quiz F(A,B,C,D) =  m(0,2,3,5,6,7,8,10,11,14,15) F = D A B A B C D 0000 1111 1000 0111 10011001 010001000 11 11 C

29. 9/16/04UCB EECS150 D. Culler Fa04 29 C+ B’D’ find the smallest number of the largest possible subcubes to cover the ON-set (fewer terms with fewer inputs per term) Karnaugh map: 4-variable example F(A,B,C,D) =  m(0,2,3,5,6,7,8,10,11,14,15) F = D A B A B C D 0000 1111 1000 0111 10011001 010001000 11 11 C + A’BD

30. 9/16/04UCB EECS150 D. Culler Fa04 30 + B’C’D Karnaugh maps: don’t cares f(A,B,C,D) =  m(1,3,5,7,9) + d(6,12,13) –without don't cares »f = 01 X0X1X0X1 D A1 110X110X 00 B C A’D

31. 9/16/04UCB EECS150 D. Culler Fa04 31 Karnaugh maps: don’t cares (cont’d) f(A,B,C,D) =  m(1,3,5,7,9) + d(6,12,13) –f = A'D + B'C'Dwithout don't cares –f = with don't cares don't cares can be treated as 1s or 0s depending on which is more advantageous 01 X0X1X0X1 D A1 110X110X 00 B C A'D by using don't care as a "1" a 2-cube can be formed rather than a 1-cube to cover this node + C'D

32. 9/16/04UCB EECS150 D. Culler Fa04 32 we'll need a 4-variable Karnaugh map for each of the 3 output functions Design example: two-bit comparator block diagram LT EQ GT A B C D A B C D N1 N2 ABCDLTEQGT 0000010 01100 10100 11100 0100001 01010 10100 11100 1000001 01001 10010 11100 1100001 01001 10001 11010 and truth table

33. 9/16/04UCB EECS150 D. Culler Fa04 33 A' B' D + A' C + B' C D B C' D' + A C' + A B D' LT= EQ= GT= K-map for EQK-map for LTK-map for GT Design example: two-bit comparator (cont’d) 0 00100010 00 D A11 010001000 B C 10011001 00 D A00 10011001 B C 010001000 11 D A00 0 00100010 B C = (A xnor C) (B xnor D) LT and GT are similar (flip A/C and B/D) A'B'C'D' + A'BC'D + ABCD + AB'CD’ Canonical PofS vs minimal?

34. 9/16/04UCB EECS150 D. Culler Fa04 34 two alternative implementations of EQ with and without XOR XNOR is implemented with at least 3 simple gates Design example: two-bit comparator (cont’d)

35. 9/16/04UCB EECS150 D. Culler Fa04 35 block diagram and truth table 4-variable K-map for each of the 4 output functions A2A1B2B1P8P4P2P1 00000000 010000 100000 110000 01000000 010001 100010 110011 10000000 010010 100100 110110 11000000 010011 100110 111001 Design example: 2x2-bit multiplier P1 P2 P4 P8 A1 A2 B1 B2

36. 9/16/04UCB EECS150 D. Culler Fa04 36 K-map for P8 K-map for P4 K-map for P2K-map for P1 Design example: 2x2-bit multiplier (cont’d) 00 00 B1 A200 011101111 A1 B2 0 00010001 0 00100010 B1 A2 010001000 100010000 A1 B2 00 01 B1 A2 01010101 01100110 A1 B2 00 00 B1 A200 100010000 A1 B2 P8 = A2A1B2B1 P4= A2B2B1' + A2A1'B2 P2= A2'A1B2 + A1B2B1' + A2B2'B1 + A2A1'B1 P1= A1B1

37. 9/16/04UCB EECS150 D. Culler Fa04 37 I8I4I2I1O8O4O2O1 00000001 00010010 00100011 00110100 01000101 01010110 01100111 01111000 10001001 10010000 1010XXXX 1011XXXX 1100XXXX 1101XXXX 1110XXXX 1111XXXX block diagram and truth table 4-variable K-map for each of the 4 output functions O1 O2 O4 O8 I1 I2 I4 I8 Design example: BCD increment by 1

38. 9/16/04UCB EECS150 D. Culler Fa04 38 O8 = I4 I2 I1 + I8 I1' O4 = I4 I2' + I4 I1' + I4’ I2 I1 O2 = I8’ I2’ I1 + I2 I1' O1 = I1' O8 O4 O2 O1 Design example: BCD increment by 1 (cont’d) 00 X1X0X1X0 I1 I8 010001000 XX I4 I2 01 X0X0X0X0 I1 I801 XX I4 I2 01010101 X0X0X0X0 I1 I8 10011001 XX I4 I2 10 X1X0X1X0 I1 I801 XX I4 I2

39. 9/16/04UCB EECS150 D. Culler Fa04 39 Definition of terms for two-level simplification Implicant –Single element of ON-set or DC-set or any group of these elements that can be combined to form a subcube Prime implicant –Implicant that can't be combined with another to form a larger subcube Essential prime implicant –Prime implicant is essential if it alone covers an element of ON-set –Will participate in ALL possible covers of the ON-set –DC-set used to form prime implicants but not to make implicant essential Objective: –Grow implicant into prime implicants (minimize literals per term) –Cover the ON-set with as few prime implicants as possible (minimize number of product terms)

40. 9/16/04UCB EECS150 D. Culler Fa04 40 0X110X111 10101010 D A 100010000 11 B C 5 prime implicants: BD, ABC', ACD, A'BC, A'C'D Examples to illustrate terms 01 10101010 D A 01010101 10 B C 6 prime implicants: A'B'D, BC', AC, A'C'D, AB, B'CD minimum cover: AC + BC' + A'B'D essential minimum cover: 4 essential implicants essential

41. 9/16/04UCB EECS150 D. Culler Fa04 41 Algorithm for two-level simplification Algorithm: minimum sum-of-products expression from a Karnaugh map –Step 1: choose an element of the ON-set –Step 2: find "maximal" groupings of 1s and Xs adjacent to that element »consider top/bottom row, left/right column, and corner adjacencies »this forms prime implicants (number of elements always a power of 2) –Repeat Steps 1 and 2 to find all prime implicants –Step 3: revisit the 1s in the K-map »if covered by single prime implicant, it is essential, and participates in final cover »1s covered by essential prime implicant do not need to be revisited –Step 4: if there remain 1s not covered by essential prime implicants »select the smallest number of prime implicants that cover the remaining 1s

42. 9/16/04UCB EECS150 D. Culler Fa04 42 X101X101 011101111 D A 0X010X01 X001X001 B C 3 primes around AB'C'D' Algorithm for two-level simplification (example) X101X101 011101111 D A 0X010X01 X001X001 B C 2 primes around A'BC'D' X101X101 011101111 D A 0X010X01 X001X001 B C 2 primes around ABC'D X101X101 011101111 D A 0X010X01 X001X001 B C minimum cover (3 primes) X101X101 011101111 D A 0X010X01 X001X001 B C X101X101 011101111 D A 0X010X01 X001X001 B C 2 essential primes X101X101 011101111 D A 0X010X01 X001X001 B C

43. 9/16/04UCB EECS150 D. Culler Fa04 43 Summary Boolean Algebra provides framework for logic simplification De Morgans transforms between gate types Uniting to reduce minterms Karnaugh maps provide visual notion of simplifications Algorithm for producing reduced form. Question: are there programmable logic families that are simpler than FPGAs for the canonical forms?