1. Lecture 27 Computer Architecture Adapted From: Supercomputing in Plain English Part VII: Multicore Madness Henry Neeman, Director OU Supercomputing Center for Education & Research University of Oklahoma Wednesday October 17 2007

2. Supercomputing in Plain English: Multicore Madness Wednesday October 17 2007 2 Outline The March of Progress Multicore/Many-core Basics Software Strategies for Multicore/Many-core A Concrete Example: Weather Forecasting

3. The March of Progress

4. Supercomputing in Plain English: Multicore Madness Wednesday October 17 2007 4 10 racks @ 1000 lbs per rack 270 Pentium4 Xeon CPUs, 2.0 GHz, 512 KB L2 cache 270 GB RAM, 400 MHz FSB 8 TB disk Myrinet2000 Interconnect 100 Mbps Ethernet Interconnect OS: Red Hat Linux Peak speed: 1.08 TFLOP/s (1.08 trillion calculations per second) One of the first Pentium4 clusters! OU’s TeraFLOP Cluster, 2002 boomer.oscer.ou.edu

5. Supercomputing in Plain English: Multicore Madness Wednesday October 17 2007 5 TeraFLOP, Prototype 2006, Sale 2011 http://news.com.com/2300-1006_3-6119652.html 9 years from room to chip!

6. Supercomputing in Plain English: Multicore Madness Wednesday October 17 2007 6 Moore’s Law In 1965, Gordon Moore was an engineer at Fairchild Semiconductor. He noticed that the number of transistors that could be squeezed onto a chip was doubling about every 18 months. It turns out that computer speed is roughly proportional to the number of transistors per unit area. Moore wrote a paper about this concept, which became known as “Moore’s Law.”

7. Supercomputing in Plain English: Multicore Madness Wednesday October 17 2007 7 Moore’s Law in Practice Year log(Speed) CPU

8. Supercomputing in Plain English: Multicore Madness Wednesday October 17 2007 8 Moore’s Law in Practice Year log(Speed) CPU Network Bandwidth

9. Supercomputing in Plain English: Multicore Madness Wednesday October 17 2007 9 Moore’s Law in Practice Year log(Speed) CPU Network Bandwidth RAM

10. Supercomputing in Plain English: Multicore Madness Wednesday October 17 2007 10 Moore’s Law in Practice Year log(Speed) CPU Network Bandwidth RAM 1/Network Latency

11. Supercomputing in Plain English: Multicore Madness Wednesday October 17 2007 11 Moore’s Law in Practice Year log(Speed) CPU Network Bandwidth RAM 1/Network Latency Software

12. Supercomputing in Plain English: Multicore Madness Wednesday October 17 2007 12 Fastest Supercomputer vs. Moore www.top500.org

13. The Tyranny of the Storage Hierarchy

14. Supercomputing in Plain English: Multicore Madness Wednesday October 17 2007 14 The Storage Hierarchy Registers Cache memory Main memory (RAM) Hard disk Removable media (e.g., DVD) Internet Fast, expensive, few Slow, cheap, a lot [5] [6]

15. Supercomputing in Plain English: Multicore Madness Wednesday October 17 2007 15 RAM is Slow CPU 351 GB/sec [7] 10.66 GB/sec [9] (3%) Bottleneck The speed of data transfer between Main Memory and the CPU is much slower than the speed of calculating, so the CPU spends most of its time waiting for data to come in or go out.

16. Supercomputing in Plain English: Multicore Madness Wednesday October 17 2007 16 Why Have Cache? CPU Cache is nearly the same speed as the CPU, so the CPU doesn’t have to wait nearly as long for stuff that’s already in cache: it can do more operations per second! 351 GB/sec [7] 10.66 GB/sec [9] (3%) 253 GB/sec [8] (72%)

17. Supercomputing in Plain English: Multicore Madness Wednesday October 17 2007 17 Storage Use Strategies Register reuse: Do a lot of work on the same data before working on new data. Cache reuse: The program is much more efficient if all of the data and instructions fit in cache; if not, try to use what’s in cache a lot before using anything that isn’t in cache. Data locality: Try to access data that are near each other in memory before data that are far. I/O efficiency: Do a bunch of I/O all at once rather than a little bit at a time; don’t mix calculations and I/O.

18. Supercomputing in Plain English: Multicore Madness Wednesday October 17 2007 18 A Concrete Example OSCER’s big cluster, topdawg, has Irwindale CPUs: single core, 3.2 GHz, 800 MHz Front Side Bus. The theoretical peak CPU speed is 6.4 GFLOPs (double precision) per CPU, and in practice we’ve gotten as high as 94% of that. So, in theory each CPU could consume 143 GB/sec. The theoretical peak RAM bandwidth is 6.4 GB/sec, but in practice we get about half that. So, any code that does less than 45 calculations per byte transferred between RAM and cache has speed limited by RAM bandwidth.

19. Good Cache Reuse Example

20. Supercomputing in Plain English: Multicore Madness Wednesday October 17 2007 20 A Sample Application Matrix-Matrix Multiply Let A, B and C be matrices of sizes nr  nc, nr  nk and nk  nc, respectively: The definition of A = B C is for r  {1, nr}, c  {1, nc}.

21. Supercomputing in Plain English: Multicore Madness Wednesday October 17 2007 21 Matrix Multiply: Naïve Version SUBROUTINE matrix_matrix_mult_naive (dst, src1, src2, & & nr, nc, nq) IMPLICIT NONE INTEGER,INTENT(IN) :: nr, nc, nq REAL,DIMENSION(nr,nc),INTENT(OUT) :: dst REAL,DIMENSION(nr,nq),INTENT(IN) :: src1 REAL,DIMENSION(nq,nc),INTENT(IN) :: src2 INTEGER :: r, c, q DO c = 1, nc DO r = 1, nr dst(r,c) = 0.0 DO q = 1, nq dst(r,c) = dst(r,c) + src1(r,q) * src2(q,c) END DO END SUBROUTINE matrix_matrix_mult_naive

22. Supercomputing in Plain English: Multicore Madness Wednesday October 17 2007 22 Performance of Matrix Multiply Better

23. Supercomputing in Plain English: Multicore Madness Wednesday October 17 2007 23 Tiling

24. Supercomputing in Plain English: Multicore Madness Wednesday October 17 2007 24 Tiling Tile: A small rectangular subdomain of a problem domain. Sometimes called a block or a chunk. Tiling: Breaking the domain into tiles. Tiling strategy: Operate on each tile to completion, then move to the next tile. Tile size can be set at runtime, according to what’s best for the machine that you’re running on.

25. Supercomputing in Plain English: Multicore Madness Wednesday October 17 2007 25 Tiling Code SUBROUTINE matrix_matrix_mult_by_tiling (dst, src1, src2, nr, nc, nq, & & rtilesize, ctilesize, qtilesize) IMPLICIT NONE INTEGER,INTENT(IN) :: nr, nc, nq REAL,DIMENSION(nr,nc),INTENT(OUT) :: dst REAL,DIMENSION(nr,nq),INTENT(IN) :: src1 REAL,DIMENSION(nq,nc),INTENT(IN) :: src2 INTEGER,INTENT(IN) :: rtilesize, ctilesize, qtilesize INTEGER :: rstart, rend, cstart, cend, qstart, qend DO cstart = 1, nc, ctilesize cend = cstart + ctilesize - 1 IF (cend > nc) cend = nc DO rstart = 1, nr, rtilesize rend = rstart + rtilesize - 1 IF (rend > nr) rend = nr DO qstart = 1, nq, qtilesize qend = qstart + qtilesize - 1 IF (qend > nq) qend = nq CALL matrix_matrix_mult_tile(dst, src1, src2, nr, nc, nq, & & rstart, rend, cstart, cend, qstart, qend) END DO END SUBROUTINE matrix_matrix_mult_by_tiling

26. Supercomputing in Plain English: Multicore Madness Wednesday October 17 2007 26 Multiplying Within a Tile SUBROUTINE matrix_matrix_mult_tile (dst, src1, src2, nr, nc, nq, & & rstart, rend, cstart, cend, qstart, qend) IMPLICIT NONE INTEGER,INTENT(IN) :: nr, nc, nq REAL,DIMENSION(nr,nc),INTENT(OUT) :: dst REAL,DIMENSION(nr,nq),INTENT(IN) :: src1 REAL,DIMENSION(nq,nc),INTENT(IN) :: src2 INTEGER,INTENT(IN) :: rstart, rend, cstart, cend, qstart, qend INTEGER :: r, c, q DO c = cstart, cend DO r = rstart, rend IF (qstart == 1) dst(r,c) = 0.0 DO q = qstart, qend dst(r,c) = dst(r,c) + src1(r,q) * src2(q,c) END DO END SUBROUTINE matrix_matrix_mult_tile

27. Supercomputing in Plain English: Multicore Madness Wednesday October 17 2007 27 Reminder: Naïve Version, Again SUBROUTINE matrix_matrix_mult_naive (dst, src1, src2, & & nr, nc, nq) IMPLICIT NONE INTEGER,INTENT(IN) :: nr, nc, nq REAL,DIMENSION(nr,nc),INTENT(OUT) :: dst REAL,DIMENSION(nr,nq),INTENT(IN) :: src1 REAL,DIMENSION(nq,nc),INTENT(IN) :: src2 INTEGER :: r, c, q DO c = 1, nc DO r = 1, nr dst(r,c) = 0.0 DO q = 1, nq dst(r,c) = dst(r,c) + src1(r,q) * src2(q,c) END DO END SUBROUTINE matrix_matrix_mult_naive

28. Supercomputing in Plain English: Multicore Madness Wednesday October 17 2007 28 Performance with Tiling Better

29. Supercomputing in Plain English: Multicore Madness Wednesday October 17 2007 29 The Advantages of Tiling It allows your code to exploit data locality better, to get much more cache reuse: your code runs faster! It’s a relatively modest amount of extra coding (typically a few wrapper functions and some changes to loop bounds). If you don’t need tiling – because of the hardware, the compiler or the problem size – then you can turn it off by simply setting the tile size equal to the problem size.

30. Supercomputing in Plain English: Multicore Madness Wednesday October 17 2007 30 Why Does Tiling Work Here? Cache optimization works best when the number of calculations per byte is large. For example, with matrix-matrix multiply on an n × n matrix, there are O(n 3 ) calculations (on the order of n 3 ), but only O(n 2 ) bytes of data. So, for large n, there are a huge number of calculations per byte transferred between RAM and cache.

31. Multicore/Many-core Basics

32. Supercomputing in Plain English: Multicore Madness Wednesday October 17 2007 32 What is Multicore? In the olden days (i.e., the first half of 2005), each CPU chip had one “brain” in it. More recently, each CPU chip has 2 cores (brains), and, starting in late 2006, 4 cores. Jargon: Each CPU chip plugs into a socket, so these days, to avoid confusion, people refer to sockets and cores, rather than CPUs or processors. Each core is just like a full blown CPU, except that it shares its socket with one or more other cores – and therefore shares its bandwidth to RAM.

33. Supercomputing in Plain English: Multicore Madness Wednesday October 17 2007 33 Dual Core Core

34. Supercomputing in Plain English: Multicore Madness Wednesday October 17 2007 34 Quad Core Core

35. Supercomputing in Plain English: Multicore Madness Wednesday October 17 2007 35 Oct Core Core Core

36. Supercomputing in Plain English: Multicore Madness Wednesday October 17 2007 36 The Challenge of Multicore: RAM Each socket has access to a certain amount of RAM, at a fixed RAM bandwidth per SOCKET. As the number of cores per socket increases, the contention for RAM bandwidth increases too. At 2 cores in a socket, this problem isn’t too bad. But at 16 or 32 or 80 cores, it’s a huge problem. So, applications that are cache optimized will get big speedups. But, applications whose performance is limited by RAM bandwidth are going to speed up only as fast as RAM bandwidth speeds up. RAM bandwidth speeds up much slower than CPU speeds up.

37. Supercomputing in Plain English: Multicore Madness Wednesday October 17 2007 37 The Challenge of Multicore: Network Each node has access to a certain number of network ports, at a fixed number of network ports per NODE. As the number of cores per node increases, the contention for network ports increases too. At 2 cores in a socket, this problem isn’t too bad. But at 16 or 32 or 80 cores, it’s a huge problem. So, applications that do minimal communication will get big speedups. But, applications whose performance is limited by the number of MPI messages are going to speed up very very little – and may even crash the node.

38. Supercomputing in Plain English: Multicore Madness Wednesday October 17 2007 38 Multicore/Many-core Problem Most multicore chip families have relatively small cache per core (e.g., 2 MB) – and this problem seems likely to remain. Small TLBs make the problem worse: 512 KB per core rather than 2 MB. So, to get good cache reuse, you need to partition algorithm so subproblem needs no more than 512 KB.

39. Supercomputing in Plain English: Multicore Madness Wednesday October 17 2007 39 The T.L.B. on a Current Chip On Intel Core Duo (“Yonah”): Cache size is 2 MB per core. Page size is 4 KB. A core’s data TLB size is 128 page table entries. Therefore, D-TLB only covers 512 KB of cache.

40. Supercomputing in Plain English: Multicore Madness Wednesday October 17 2007 40 The T.L.B. on a Current Chip On Intel Core Duo (“Yonah”): Cache size is 2 MB per core. Page size is 4 KB. A core’s data TLB size is 128 page table entries. Therefore, D-TLB only covers 512 KB of cache. The cost of a TLB miss is 49 cycles, equivalent to as many as 196 calculations! (4 FLOPs per cycle) http://www.digit-life.com/articles2/cpu/rmma-via-c7.html

41. Supercomputing in Plain English: Multicore Madness Wednesday October 17 2007 41 What Do We Need? We need much bigger caches! TLB must be big enough to cover the entire cache. It’d be nice to have RAM speed increase as fast as core counts increase, but let’s not kid ourselves.

42. Supercomputing in Plain English: Multicore Madness Wednesday October 17 2007 42 To Learn More Supercomputing http://www.oscer.ou.edu/education.php

43. Computer Architecture Spring 2012 Lecture 27. CMPs & SMTs Adapted from Mary Jane Irwin ( www.cse.psu.edu/~mji )www.cse.psu.edu/~mji [Adapted from Computer Organization and Design, Patterson & Hennessy, © 2005]

44. Multithreading on A Chip  Find a way to “hide” true data dependency stalls, cache miss stalls, and branch stalls by finding instructions (from other process threads) that are independent of those stalling instructions  Multithreading – increase the utilization of resources on a chip by allowing multiple processes (threads) to share the functional units of a single processor l Processor must duplicate the state hardware for each thread – a separate register file, PC, instruction buffer, and store buffer for each thread l The caches, TLBs, BHT, BTB can be shared (although the miss rates may increase if they are not sized accordingly) l The memory can be shared through virtual memory mechanisms l Hardware must support efficient thread context switching

45. Types of Multithreading on a Chip  Fine-grain – switch threads on every instruction issue l Round-robin thread interleaving (skipping stalled threads) l Processor must be able to switch threads on every clock cycle l Advantage – can hide throughput losses that come from both short and long stalls l Disadvantage – slows down the execution of an individual thread since a thread that is ready to execute without stalls is delayed by instructions from other threads  Coarse-grain – switches threads only on costly stalls (e.g., L2 cache misses) l Advantages – thread switching doesn’t have to be essentially free and much less likely to slow down the execution of an individual thread l Disadvantage – limited, due to pipeline start-up costs, in its ability to overcome throughput loss -Pipeline must be flushed and refilled on thread switches

46. Simultaneous Multithreading (SMT)  A variation on multithreading that uses the resources of a multiple-issue, dynamically scheduled processor (superscalar) to exploit both program ILP and thread- level parallelism (TLP) l Most SS processors have more machine level parallelism than most programs can effectively use (i.e., than have ILP) l With register renaming and dynamic scheduling, multiple instructions from independent threads can be issued without regard to dependencies among them -Need separate rename tables (ROBs) for each thread -Need the capability to commit from multiple threads (i.e., from multiple ROBs) in one cycle  Intel’s Pentium 4 SMT called hyperthreading l Supports just two threads (doubles the architecture state) l Typically, each core of newer multi-core process is hyperthreaded

47. Threading on a 4-way SS Processor Example Thread AThread B Thread CThread D Time → Issue slots → SMTFine MTCoarse MT

48. William Stallings Computer Organization and Architecture 8 th Edition Chapter 18 Multicore Computers

49. Hardware Performance Issues  Microprocessors have seen an exponential increase in performance l Improved organization l Increased clock frequency  Increase in Parallelism l Pipelining l Superscalar l Simultaneous multithreading (SMT)  Diminishing returns l More complexity requires more logic l Increasing chip area for coordinating and signal transfer logic -Harder to design, make and debug

50. Alternative Chip Organizations

51. Intel Hardware Trends

52. Increased Complexity  Power requirements grow exponentially with chip density and clock frequency l Can use more chip area for cache -Smaller -Order of magnitude lower power requirements  By 2015 l 100 billion transistors on 300mm 2 die -Cache of 100MB -1 billion transistors for logic  Pollack’s rule: l Performance is roughly proportional to square root of increase in complexity -Double complexity gives 40% more performance  Multicore has potential for near-linear improvement  Unlikely that one core can use all cache effectively

53. Power and Memory Considerations

54. Chip Utilization of Transistors

55. Software Performance Issues  Performance benefits dependent on effective exploitation of parallel resources  Even small amounts of serial code impact performance l 10% inherently serial on 8 processor system gives only 4.7 times performance  Communication, distribution of work and cache coherence overheads  Some applications effectively exploit multicore processors

56. Effective Applications for Multicore Processors  Database  Servers handling independent transactions  Multi-threaded native applications l Lotus Domino, Siebel CRM  Multi-process applications l Oracle, SAP, PeopleSoft  Java applications l Java VM is multi-thread with scheduling and memory management l Sun’s Java Application Server, BEA’s Weblogic, IBM Websphere, Tomcat  Multi-instance applications l One application running multiple times  E.g. Value Game Software

57. Multicore Organization  Number of core processors on chip  Number of levels of cache on chip  Amount of shared cache  Next slide examples of each organization:  (a) ARM11 MPCore (deleted)  (b) AMD Opteron (deleted)  (c) Intel Core Duo  (d) Intel Core i7

58. Multicore Organization Alternatives

59. Advantages of shared L2 Cache  Constructive interference reduces overall miss rate  Data shared by multiple cores not replicated at cache level  With proper frame replacement algorithms mean amount of shared cache dedicated to each core is dynamic l Threads with less locality can have more cache  Easy inter-process communication through shared memory  Cache coherency confined to L1  Dedicated L2 cache gives each core more rapid access l Good for threads with strong locality  Shared L3 cache may also improve performance

60. Individual Core Architecture  Intel Core Duo uses superscalar cores  Intel Core i7 uses simultaneous multi-threading (SMT) l Scales up number of threads supported -4 SMT cores, each supporting 4 threads appears as 16 core

61. Intel x86 Multicore Organization - Core Duo (1)  2006  Two x86 superscalar, shared L2 cache  Dedicated L1 cache per core l 32KB instruction and 32KB data  Thermal control unit per core l Manages chip heat dissipation l Maximize performance within constraints l Improved ergonomics  Advanced Programmable Interrupt Controlled (APIC) l Inter-process interrupts between cores l Routes interrupts to appropriate core l Includes timer so OS can interrupt core

62. Intel x86 Multicore Organization - Core Duo (2)  Power Management Logic l Monitors thermal conditions and CPU activity l Adjusts voltage and power consumption l Can switch individual logic subsystems  2MB shared L2 cache l Dynamic allocation l MESI support for L1 caches l Extended to support multiple Core Duo in SMP -L2 data shared between local cores or external  Bus interface

63. Intel Core Duo Block Diagram

64. Intel x86 Multicore Organization - Core i7  November 2008  Four x86 SMT processors  Dedicated L2, shared L3 cache  Speculative pre-fetch for caches  On chip DDR3 memory controller l Three 8 byte channels (192 bits) giving 32GB/s l No front side bus  QuickPath Interconnection l Cache coherent point-to-point link l High speed communications between processor chips l 6.4G transfers per second, 16 bits per transfer l Dedicated bi-directional pairs l Total bandwidth 25.6GB/s

65. Intel Core i7 Block Diagram

66. Performance Effect of Multiple Cores

67. Computer Architecture Adapted from Mary Jane Irwin ( www.cse.psu.edu/~mji )www.cse.psu.edu/~mji [Adapted from Computer Organization and Design, Patterson & Hennessy, © 2005]

68. Multicore Xbox360 – “Xenon” processor  To provide game developers with a balanced and powerful platform l Three SMT processors, 32KB L1 D$ & I$, 1MB UL2 cache l 165M transistors total l 3.2 Ghz Near-POWER ISA l 2-issue, 21 stage pipeline, with 128 128-bit registers l Weak branch prediction – supported by software hinting l In order instructions l Narrow cores – 2 INT units, 2 128-bit VMX units, 1 of anything else  An ATI-designed 500MZ GPU w/ 512MB of DDR3DRAM l 337M transistors, 10MB framebuffer l 48 pixel shader cores, each with 4 ALUs

69. Xenon Diagram Core 0 L1D L1I Core 1 L1D L1I Core 2 L1D L1I 1MB UL2 512MB DRAM GPU BIU/IO Intf 3D Core 10MB EDRAM Video Out MC0 MC1 Analog Chip XMA Dec SMC DVD HDD Port Front USBs (2) Wireless MU ports (2 USBs) Rear USB (1) Ethernet IR Audio Out Flash Systems Control Video Out

70. The PS3 “Cell” Processor Architecture  Composed of a Non-SMP Architecture l 234M transistors @ 4Ghz l 1 Power Processing Element, 8 “Synergistic” (SIMD) PE’s l 512KB L2 $ - Massively high bandwidth (200GB/s) bus connects it to everything else l The PPE is strangely similar to one of the Xenon cores -Almost identical, really. Slight ISA differences, and fine-grained MT instead of real SMT l The real differences lie in the SPEs (21M transistors each) -An attempt to ‘fix’ the memory latency problem by giving each processor complete control over it’s own 256KB “scratchpad” – 14M transistors –Direct mapped for low latency -4 vector units per SPE, 1 of everything else – 7M trans.

71. The PS3 “Cell” Processor Architecture

72. How to make use of the SPEs

73. What about the Software?  Makes use of special IBM “Hypervisor” l Like an OS for OS’s l Runs both a real time OS (for sound) and non-real time (for things like AI)  Software must be specially coded to run well l The single PPE will be quickly bogged down l Must make use of SPEs wherever possible l This isn’t easy, by any standard  What about Microsoft? l Development suite identifies which 6 threads you’re expected to run l Four of them are DirectX based, and handled by the OS l Only need to write two threads, functionally  http://ps3forums.com/showthread.php?t=22858 http://ps3forums.com/showthread.php?t=22858

74. Next Lecture and Reminders  Reminders l Final is Wednesday, May 2 from 1-2:50 PM in ITT 328