1. CLEMSON U N I V E R S I T Y AVR32 Micro Controller Unit Atmel has created the first processor architected specifically for 21st century applications that require both performance and low power consumption. The Harvard architecture and multiple high-speed system buses guarantee exceptional processing performance whilst various sleeping modes and Dynamic Frequency Scaling ensures low power consumption.

2. CLEMSON U N I V E R S I T Y Basic Features 32-bit RISC microprocessor core Handles 32-bit and 64-bit applications 166 MHz processor speed AVR32B contains dedicated hardware for storing interrupt register values, AVR32A go to system stack. So, AVR32A handles interrupts slower than AVR32B

3. CLEMSON U N I V E R S I T Y Design Goals Eliminates non-productive processor cycles using the following techniques: Reducing the number of load/store cycles. Maximizing the utilization of computational resources. Providing zero-penalty branches. Reducing the number of cache misses.

4. CLEMSON U N I V E R S I T Y On-board DSP Provides SIMD(Single Instruction, Multiple Data) and DSP instruction sets DSPs are self-contained processors with their own instruction set SIMD-extensions rely on the general-purpose portions of the CPU Can execute MPEG4 decoding at 30 fps at 100 MHz while comparable architectures require 260 MHz.

5. CLEMSON U N I V E R S I T Y Reducing Load/Store It can take 14 cycles to execute a Single Instruction on a conventional processor The AVR32 has a 'load with extracted index' instruction that reduces this operation to just 7 cycles

6. CLEMSON U N I V E R S I T Y Pipelining 7-stage pipeline with three sub pipelines (multiplication, ALU, load/store) that allow arithmetic operations on non- dependent data to be executed out of order and in parallel.

7. CLEMSON U N I V E R S I T Y Reducing Cache Misses AVR32 code density is 10% to 50% more dense than that of ARM9 or ARM11 cores. Denser code allows more instructions to be stored in the processor cache, thereby reducing the number of cache misses and increasing overall processor throughput per cycle.

8. CLEMSON U N I V E R S I T Y Low Power Consumption The traditional technique to increase computational power is to increase the clock speed, which increases power consumption AVR architecture executes more DSP operations per clock cycle, so it can achieve the higher computational throughput, with a low clock frequency and low power consumption (40μA in sleep mode and 600μA/MHz in active mode)

9. CLEMSON U N I V E R S I T Y Target Uses and Development Board Appliance control Security systems Industrial control and Automation PC peripherals Handheld Video Players Medical Equip.