1. Nectar F2F, Barcelona 2013-09 10/8/2015K.-H. Sulanke, DESY1 Digital Camera Trigger Status September 2013 K.-H. Sulanke DESY

2. Nectar F2F, Barcelona 2013-09 10/8/2015K.-H. Sulanke, DESY2 The Digital Trigger Schema L0, 7 pixel, mezzanine board, very low noise preamp + comparator + DAC L1, 37 pixel, Digital Trigger backplane, based on Xilinx-Spartan 6 FPGAs L2, is a crate, ~ 50 x 20 x 20 cm, ~ 11 kg –18 x CSB (Cluster Service Board) –1 x L2CB (L2 Controller Board) Ethernet interface Optical / electrical camera trigger output PMT = Photomultiplier Tube FEB = Frontend Board DTB = Digital Trigger Backplane CSB = Cluster Service Board L2CB = L2 Controller Board L0 FEB DTB FPGA PMT L1 CSB L2 #01 … #16 L0 FEB FPGA L1 Sector_trig #01 … #18 FPGA Camera_trig GPS_clock PMT ethernet L2CB 77 7 7 L0_neighbor 24V (optional)

3. Nectar F2F, Barcelona 2013-09 10/8/2015K.-H. Sulanke, DESY3 New Boards Developed in 2013 Digital Trigger Backplane L0 Mezzanine L0 Testboard

4. Nectar F2F, Barcelona 2013-09 10/8/2015K.-H. Sulanke, DESY4 Digital Trigger L0 Mezzanine Board Preamp LVDS Comparator Diff. Analog in LVDS out Schematic simulated, very low noise preamplifier Two PCBs, a DRAGON - and a NECTAR - version 5 + 5 L0 boards assembled Trigger threshold DAC Opamp Comp Digital L0 Mezzanine LVDS

5. Nectar F2F, Barcelona 2013-09 10/8/2015K.-H. Sulanke, DESY5 L0 Mezzanine Board, Dragon Version 6 layer PCB with length-tuned signal lines Preamplifier Trigger- Treshold-DAC Comparator

6. Nectar F2F, Barcelona 2013-09 10/8/2015K.-H. Sulanke, DESY6 L0 Test Results DAC SPI interface √ (No noticeable) channel to channel skew < 100ps Minimum input signal amplitude is 2mV (L0 gain=5, presently) Minimum signal width is about 1.2 ns Crosstalk could not be seen Power consumption 160mW / channel

7. Nectar F2F, Barcelona 2013-09 10/8/2015K.-H. Sulanke, DESY7 L0 Mezzanine Board, 2nd Nectar Version 5 of 15 PCBs assembled Analog and digital part functional (tested separately) Comprehensive test (w. L0-Testboard) soon, waiting for a cable adapter

8. Nectar F2F, Barcelona 2013-09 10/8/2015K.-H. Sulanke, DESY8 Digital Trigger L0 Test Board DAC Opamp Comp FPGA Dig.Trigger-Bpl. FPGA FE-board interface L0-Testboard 7 6x5 L0 by surr. clusters Digital L0 Mezzanine L0 LVDS PMT or Pulse-Gen. Single ended to diff. Opamp RS-232

9. Nectar F2F, Barcelona 2013-09 10/8/2015K.-H. Sulanke, DESY9 Digital Trigger L0 Test Board, cont. 120 mm x 260 mm, 6 Layer PCB, various analog and digital test points Xilinx FE-board Interface Connector Analog Inputs (Lemo) RS232 / 485 interface Test Points L0-MezzaninePreamp s

10. Nectar F2F, Barcelona 2013-09 10/8/2015K.-H. Sulanke, DESY10 L0 Test Board, cont. The board has up to 8 address jumpers / CMOS_IO test pins –Using the RS485 interface allows to run up to 256 boards in parallel –7 boards to test the L1 trigger with real signals (independent on FEB) –Needs single ended analog (PMT ?) signals, positive or negative polarity (by jumper setting) presently, control via RS232 (+putty), 3-letter commands, syntax, e.g. : –„ver 2“ => check for board #2 and firmware version –„dac 1 5 234“ => set DAC, board #1, channel #5, to 234 mV Primarily for the evaluation / test of the L0 boards, but also … DT backplane (L1) to FEB interface, test of all signals possible Testing of trigger firmware modules, e.g. in system delay tuning –„del 1 3 145“ => set delay of board #1, channel #3 to ~ 145 * 35ps

11. Nectar F2F, Barcelona 2013-09 10/8/2015K.-H. Sulanke, DESY11 The Digital Trigger Backplane Rev. 2 power ethernet Frontend board connector L0 in /out and... connectors to neighbor clusters RJ-45 Xilinx FPGA vreg flash 24V ethernet power CLK PPS L0_trigger trigger IP_addr HV_ena SPI / JTAG calib_cyc reserved flash osc clock (opt.+power) PPS L1_trigger_out L2_trigger_in FE-board interface, compliant to FE_BP_interface_v6.doc by Gustavo M.

12. Nectar F2F, Barcelona 2013-09 10/8/2015K.-H. Sulanke, DESY12 Digital Trigger Backplane, cont. Power_in Clock_in PPS_in L1_out L2_in Cluster-Position- ID switches Local Oscillator Xilinx Spartan-6 FPGA FE-board Gigabit port Atmel PROM (Xilinx config.) Test Port Alternative power connector FE-board 24V-fuse Local synchronous DC-DC power supply Xilinx JTAG port 64 bit ID ROM Temp. sensor FE-Board connector neighbor cluster connections

13. Nectar F2F, Barcelona 2013-09 10/8/2015K.-H. Sulanke, DESY13 Digital Trigger Backplane, Status 3 boards (of 5 PCBs) assembled by the DESY workshop Tests : –Power supply √ –Xilinx configuration via JTAG or PROM √ –Local and external clock √ –LVDS Interface (signal integrity) to neighbor clusters √ –Inverse mode (for testing), used as a 37 bit pattern generator √ Minimum (clean) signal width is 1.25 ns –Combined power / clock / pps / L1_out / L2_in RJ45-connection √ Saves cabling –Various trigger alghorithms (firmware), ongoing –distributed schema for clock / PPS / L1 (firmware), - –Temperature sensor, - –FE-board interface, -

14. Nectar F2F, Barcelona 2013-09 10/8/2015K.-H. Sulanke, DESY14 Digital Trigger as Pattern Generator Inverse mode (for testing), used as a 37 bit pattern generator Based on a look up table of e.g. 16K x 38 bit –Minimum „L0“ signal width / time resolution is 1.05 ns –Individual pixel timing mismatch (n*40ps) can be programmed Simple pattern like 3NN or more sophisticated (time distributed) can be used expected trigger Cluster 6..0

15. Nectar F2F, Barcelona 2013-09 10/8/2015K.-H. Sulanke, DESY15 Simulation w. Data extracted from trigsim L0 signals, extracted from trigsim (by S. Vorobiov) Simulated (timing simulation), but not yet tested 3NN pattern trigger latency

16. Nectar F2F, Barcelona 2013-09 10/8/2015K.-H. Sulanke, DESY16 Test Setup w. Pattern Generator pattern generator board trigger board expected and real trigger

17. Nectar F2F, Barcelona 2013-09 10/8/2015K.-H. Sulanke, DESY17 Summary The Digital Trigger Backplane supports both, a distributed and a centralized schema, for the L1 trigger, the clock and the PPS-signal Centralized trigger schema preferred by me Boards needed for a distributed schema (preferred by the analog trigger group): –Digital Trigger L0 mezzanine –Digital Trigger Backplane A lot of firmware writing and hardware testings needed now L2 hardware development with lower priority –Single CSB sufficient for a mini camera of up to 16 clusters Design progress in time with the FE-board (Nectar, Dragon) development

18. Nectar F2F, Barcelona 2013-09 10/8/2015K.-H. Sulanke, DESY18 Next Steps Comprehensive Nectar-L0 test A lot of trigger firmware testing, using the pattern generator Redesign of the Digital Trigger backplane with latest FEB-connector angle L2 design –Cluster Service Board (CSB, 16 clusters) first –… Investigating Nectar / Dragon test setups

19. Nectar F2F, Barcelona 2013-09 10/8/2015K.-H. Sulanke, DESY19 Back Up Slides

20. Nectar F2F, Barcelona 2013-09 10/8/2015K.-H. Sulanke, DESY20 Digital Trigger Backplane, Key Features Nominal power consumption: 1.5 W Weight : 95 g + 10 g cabling to neighbor clusters -> 28 kg for LST Automatic neighbor cluster recognition (border zone) Synchronous DC-DC converter (24 V to 3.0 V …) Local clock and external clock input (any diff. > 0.1V pk-pk) FPGA load by JTAG cable or PROM or remote (by FE board) 6 x bidirectional L0 signal connection with neighbor cluster Temperature sensor (allows automatic delay correction, if needed) adjustable 8 bit cluster position ID (for unique, position-independant, firmware) Gigabit ethernet pass through connection to FE-board RJ 45 connector as combined power and clock input (single cat5e cable)

21. Nectar F2F, Barcelona 2013-09 10/8/2015K.-H. Sulanke, DESY21 Digital Trigger Backplane, 8 Layer PCB PCB design by Carola Rueger DESY

22. Nectar F2F, Barcelona 2013-09 10/8/2015K.-H. Sulanke, DESY22 Combined Power and Clock Input 24V, clock, and PPS over a single wire pair requires a single cat5e cable per cluster only (+ gigabit ethernet cable) Current jumps of 0.8 A did not influence the (recovered) clock quality Cat5e - Wire Pair Standard mode Combined mode 1Clock_inClock_in / PPS_in / 24V 2PPS_inGND 3Trig_L1_out 4Trig_L2_in FE-board Gigabit port Combined Power and Clock input Ext_Clock_PPS Clock_recovered PPS_recovered Clock+pps 24V Alternative Power conn.

23. Nectar F2F, Barcelona 2013-09 Digital L0 through Frontend-Board FPGA Allows Frontend-board-FPGA with scaler uniform FPGA internal delay (by constraints) preferred Trigger threshold DAC control by trigger FPGA, optional Separate power island with software controllable shutdown doable PMT DAC Opamp Comp FPGA Dig.Trigger-Bpl. FPGA trigger Frontend-board 7 6x5 L0 by surr. clusters Digital L0 Mezzanine L0 scaler LVDS 10/8/2015K.-H. Sulanke, DESY Poff

24. Nectar F2F, Barcelona 2013-09 10/8/2015K.-H. Sulanke, DESY24 The Centralized Trigger Schema with L2 L2 also based on Xilinx-Spartan 6 FPGAs L2 is a crate, ~ 50 x 20 x 20 cm, ~ 11 kg –18 x CSB (Cluster Service Board) –1 x L2CB (L2 Controller Board) Ethernet interface Optical / electrical camera trigger output PMT = Photomultiplier Tube FEB = Frontend Board DTB = Digital Trigger Backplane CSB = Cluster Service Board L2CB = L2 Controller Board L0 FEB DTB FPGA PMT L1 CSB L2 #01 … #16 L0 FEB FPGA L1 Sector_trig #01 … #18 FPGA Camera_trig GPS_clock PMT ethernet L2CB 77 7 7 L0_neighbor 24V (optional)

25. Nectar F2F, Barcelona 2013-09 10/8/2015K.-H. Sulanke, DESY25 The Cluster Service Board (CSB) Backplane connector Xilinx FPGA vreg flash 24V CLK PPS L2 L3 sdat JTAG Clock_PPS_24V GND L1_trigger L3_trigger RJ45 Cur_mon16 x switch 16 x Cat5e cables Clock PPS L1_trigger L3_trigger Or optional, including 24V

26. Nectar F2F, Barcelona 2013-09 10/8/2015K.-H. Sulanke, DESY26 L2 Trigger Sectors, MST, Example 271 cluster shown (1897 pixel) Each sector comprises 14..16 clusters and is connected to a certain L2 board („CSB“)

27. Nectar F2F, Barcelona 2013-09 10/8/2015K.-H. Sulanke, DESY27 From 49 Pixel to 37 Pixel Regions Overlap still big enough Saves FPGA pins and money Allows daisy chained schema for clock/pps

28. Nectar F2F, Barcelona 2013-09 10/8/2015DESY28 The DTB-FPGA‘s Functionality delay 37 pixel trigger fabric fanout progr. delays PLL Xilinx Spartan 6 FPGA trigger pix_[0][6..0] pix_[1][4..0] pix_[6][4..0] clock from center cluster from surrounding clusters to surrounding clusters pix*_[0][4..0] calibrate STM to L2_trigger board FPGA

29. Nectar F2F, Barcelona 2013-09 10/8/2015K.-H. Sulanke, DESY29 DT Backplane, Basic Firmware Features 37 or 49 pixel areas, depending on the trigger / clock mode (distributed or centralized) Minimum Trigger window is 1.05 ns Individual L0 delay calibration in about 40 ps steps

30. Nectar F2F, Barcelona 2013-09 10/8/2015K.-H. Sulanke, DESY30 M12 Cat6, Combined Power / Clock Input Instead of RJ45, more robust by Harting, Molex,... To be replaced by M12