1. Programmable/Stoppable Oscillator Based on Self-Timed Rings Eslam Yahya 1,4, Oussama Elissati 1,3, Hatem Zakaria 1,4, Laurent Fesquet 1 and Marc Renaudin 2 1 TIMA Laboratory, Grenoble, France 2 TIEMPO, Montbonnot, France 3 ST-Ericsson, Grenoble, France 4 Banha High Institute of Technology, Banha, Egypt ASYNC 2009, UNC Chapel hill

2. ASYNC 2009, UNC Chapel Hill2 Context and Motivation Process variability increases drastically in the 45 nm technologies and beyond. Application of DVFS techniques is essential.  Programmable oscillators are needed Self –Timed Rings are promising solutions for:  Reconfigurability.  Process Variation. However, no programmable oscillators based on Self-Timed Rings are introduced in the literature.

3. ASYNC 2009, UNC Chapel Hill3 Outline Self-timed rings Oscillation Frequency Modeling and Calculation Architecture of Programmable Self-Timed Ring Programmable-Stoppable Oscillator Implementation and results Conclusion and Future Work

4. ASYNC 2009, UNC Chapel Hill4 CCCC D ff D rr Self-Timed Ring Tokens and bubblesPropagation rules T 1 TB 11 TB 0

5. ASYNC 2009, UNC Chapel Hill5 Two Oscillation Modes Burst mode Evenly Spaced Mode Oscillation modes

6. ASYNC 2009, UNC Chapel Hill6 Timed VHDL Model Programmable Ring  So many simulations. Contradiction between digital simulation and analog simulation. Simulating the same ring with the same number of tokens and bubbles, with tow different spatial token distributions.  Analog : same steady state waveform.  Digital : different steady state waveform. 11 stage 4 Tokens/7 Bubbles TTTTBBBBBBB TBBBBTTBBBT

7. ASYNC 2009, UNC Chapel Hill7 Charlie effect An explanation of this difference between digital and analog simulation is needed.  Charlie effect!!?? The closer the input events; the longer the propagation time, causing the separation of the tokens in the ring. 2D Charlie Diagram

8. ASYNC 2009, UNC Chapel Hill8 Timed VHDL Model 11 stage 4 Tokens/7 Bubbles TTTTBBBBBBB TBBBBTTBBBT 11 stage 4 Tokens/7 Bubbles TTTTBBBBBBB TBBBBTTBBBT Without Charlie Effect With Charlie Effect

9. ASYNC 2009, UNC Chapel Hill9 Outline Self-timed rings Oscillation Frequency Modeling and Calculation Architecture of programmable Self-Timed Ring Programmable-Stoppable Oscillator Implementation and results Conclusion and Future Work

10. ASYNC 2009, UNC Chapel Hill10 Estimating the oscillation period in Inverter Ring: Estimating the oscillation period in Self-Timed Rings: Where: s is the separation time between input events Deriving an equation: T = 4. Charlie(R) = f (D rr, D ff, R) Charlie(R) is derived. Modeling and Calculation T = 2N. DInv T = f (Drr, Dff, s) s = f (N T /N B ) T = 4. Charlie(s) R = N T /N B s = f (R)

11. ASYNC 2009, UNC Chapel Hill11 Charlie(R)   If Charlie from Charlie(s) Charlie from Charlie(R) Error < 1%

12. ASYNC 2009, UNC Chapel Hill12 Comparison with analog simulation Case Number of Stages N T /N B R=N T /N B Frequency (Electrical simulation) MHz Frequency (Model) MHz Error A1110T/1B107967970.12% B118T/3B2.66241723861.28% C116T/5B1.2390839140.15% D114T/7B0.57380237371.70% E112T/9B0.2187918910.63% F108T/2B4175117520.05% G106T/4B1.5344134761.01% H104T/6B0.67414340641.9% I102T/8B0.5208220810.04% J54T/1B4174717520.28% K52T/3B0.67413340641.67%

13. ASYNC 2009, UNC Chapel Hill13 Outline Self-timed rings Oscillation Frequency Modeling and Calculation Architecture of programmable Self-Timed Ring Programmable-Stoppable Oscillator Implementation and results Conclusion and Future Work

14. ASYNC 2009, UNC Chapel Hill14 Fixed No. of stages. Frequency is controlled by changing (N T /N B ). PSTR : Programmable Self-Timed Ring Strategy 1 ( Token/bubble configuration) C1 Set Reset C2 Stage 1 Set Reset Stage 2 Token Control Word Cn SetReset Stage n From Stage (3) From Stage (n-1) To Stage (n-1) Req Ack Req Ack

15. ASYNC 2009, UNC Chapel Hill15 PSTR : Strategy 2 Variable No. of stages with controllable N T /N B. Variable No. of stages with controllable N T /N B. C1 M1 Set Reset C2 Stage 1 M2 Set Reset Stage 2 Stage Control Word Token Control Word T1 D1 SCW0 SCW1 Cn SetReset Stage n From Stage (3) From Stage (n-1) To AND of Stage (3) To Stage (n-1) Req Ack SCW2 T2 b a b a Req Ack

16. ASYNC 2009, UNC Chapel Hill16 Outline Self-timed rings Oscillation Frequency Modeling and Calculation Architecture of programmable Self-Timed Ring (PSTR) Programmable-Stoppable Oscillator Implementation and results Conclusion and Future Work

17. ASYNC 2009, UNC Chapel Hill17 A complete architecture of PSO is designed and implemented. Asynchronous communication protocol between the processor and the PSO. The processor can Pause/Reprogram the PSO output. The protocol is taking into consideration Metastability and racings. Programmable/ Stoppable Oscillator (PSO)

18. ASYNC 2009, UNC Chapel Hill18 Interface between µ-Processor and PSO Top Control + Micro-Processor Programmable/Stoppable Oscillator “PSO” CF PC CF Reset FC CLK CFD PCD FC … Frequency Code CF … Change Frequency CFD … Change Frequency Done Signal PC … Pause Clock PCD … Pause Clock Done Signal Interface between µ-Processor and PSO

19. ASYNC 2009, UNC Chapel Hill19 Control Unit TCWSCW Stop R_out FC PC Programmable Self-Timed Ring “PSTR” C R_out CFD + Reset CFDCLK Reset FCCFReset PCD PC CF Programmable/ Stoppable Oscillator (PSO)

20. ASYNC 2009, UNC Chapel Hill20 LUT 1 Reset Stop FC CFReset LUT 2 Comparator Counter TCWSCW Count_Ref EQCF D-FF R_Out D Reset Delay 1 CFD Q PC Delay 2 Stop PCD CF Reset (Asy.) Reset (Asy.) Reset Stop EQ TCW … Token Control Word SCW … Stage Control Word R_Out … PSTR Ring Output Control Unit Stop Control Unit

21. ASYNC 2009, UNC Chapel Hill21 Outline Self-timed rings Oscillation Frequency Modeling and Calculation Architecture of programmable Self-Timed Ring(PSTR) Programmable-Stoppable Oscillator Implementation and results Conclusion and Future Work

22. ASYNC 2009, UNC Chapel Hill22 A C B DFGH Timing Diagram of the PSO

23. ASYNC 2009, UNC Chapel Hill23 Low Frequency … 10Tokens/1Bubble High Frequency … 6Tokens/5 Bubbles Analog Results of the PSO Implemented Using 45 nm STMicroelectronics Technology

24. ASYNC 2009, UNC Chapel Hill24 11 Stages Ring Strategy 1Strategy 2Strategy 3 Frequency Range 500MHz – 3GHz 400 MHz – 1.7 GHz 450 MHz – 2 GHz No. of Frequencies 5139 Step Size Irregular100 MHzIrregular Static Power 8.7 nW37.5 nW15.94 nW Dynamic Power (for 1 Bubble) 63.68 µW145 µW82.3 µW Results for Different Strategies Strategy 3: is a partial control on the number of stages

25. ASYNC 2009, UNC Chapel Hill25 Ring could not oscillate under 0.5V. A linear change of frequency from 0.8V to 1.1V. Frequency vs. Supply Voltage

26. ASYNC 2009, UNC Chapel Hill26 Montecarlo Simulation 1000 Iterations Average value of 2.6 GHz Process variability effect on the clock period: 1% Within Die 7,6% Die to Die Density Frequency 250 200 150 100 50.0 0.0 1.75 2.02.252.52.753.03.253.53.75 mu = 2.69757 sd = 205.025M N = 1000 Process Variability of the PSTR

27. ASYNC 2009, UNC Chapel Hill27 Outline Self-timed rings Oscillation Frequency Modeling and Calculation Architecture of programmable Self-Timed Ring(PSTR) Programmable-Stoppable Oscillator Implementation and results Conclusion and Future Work

28. ASYNC 2009, UNC Chapel Hill28 Self Timed Ring is used as a core of programmable oscillator. For facilitating accurate and fast design environment, timed VHDL models and Charlie(R) are introduced. Programmability is introduced to Self-Timed Rings using different strategies. PSO is designed and implemented using STMicroelectronics 45nm CMOS technology. Asynchronous handshaking protocol between the processor and the oscillator is proposed. PSO shows glitch free and no truncated clocks at its output. The implemented chip is characterized for its speed, power consumption and sensitivity to process variability. Conclusions

29. ASYNC 2009, UNC Chapel Hill29 Adding a voltage controller to the power supply. Some special implementations for high-speed C-Elements. More investigation on the phase noise. Comparing the use of PSTR and some other alternatives. Future Work

30. ASYNC 2009, UNC Chapel Hill30 Thank You