1. ECE 260B – CSE 241A Verification 1http://vlsicad.ucsd.edu ECE260B – CSE241A Winter 2005 Verification Website: http://vlsicad.ucsd.edu/courses/ece260b-w05

2. ECE 260B – CSE 241A Verification 2http://vlsicad.ucsd.edu Verification  Functional verification l Testing l Emulation l Simulation l Symbolic simulation l Formal verification  Timing verification l Testing l Simulation l STA  Physical verification l DRC l ERC l LVS  Misc l Fanout constraints, etc.

3. ECE 260B – CSE 241A Verification 3http://vlsicad.ucsd.edu Functional Verification

4. ECE 260B – CSE 241A Verification 4http://vlsicad.ucsd.edu Design Verification RTL Synthesis HDL netlist logic optimization netlist Library/ module generators physical design layout manual design specification Is design consistent with original spec? Courtesy K. Keutzer, UCB

5. ECE 260B – CSE 241A Verification 5http://vlsicad.ucsd.edu Implementation Verification RTL Synthesis HDL netlist logic optimization netlist Library/ module generators physical design layout manual design Is implementation consistent with original design intent? a b s q 0 1 d clk a b s q 0 1 d Courtesy K. Keutzer, UCB

6. ECE 260B – CSE 241A Verification 6http://vlsicad.ucsd.edu Manufacture Verification (Test) RTL Synthesis HDL netlist logic optimization netlist Library/ module generators physical design layout manual design Is manufactured circuit consistent with implemented design? a b s q 0 1 d clk a b s q 0 1 d Courtesy K. Keutzer, UCB

7. ECE 260B – CSE 241A Verification 7http://vlsicad.ucsd.edu Implementation Verification for ASICs RTL Synthesis HDL netlist logic optimization netlist Library/ module generators physical design layout manual design Apply gate-level simulation at each step to verify: (1) functionality: 0-1 behavior on regression test set (2) timing: maximum delay of circuit on critical paths a b s q 0 1 d clk a b s q 0 1 d ASIC signoff Courtesy K. Keutzer, UCB

8. ECE 260B – CSE 241A Verification 8http://vlsicad.ucsd.edu  Advantages of gate-level simulation l verifies timing and functionality simultaneously l approach well understood by designers  Disadvantages of gate-level simulation? l computationally intensive - only 1 - 10 clock cycles of 100K gate design per 1 CPU second l incomplete - results only as good as your vector set - easy to overlook incorrect timing/behavior Simulation driver (vectors) Simulation monitor (yes/no) Software Simulation a b s q 0 1 d clk Courtesy K. Keutzer, UCB

9. ECE 260B – CSE 241A Verification 9http://vlsicad.ucsd.edu Alternative - Static Signoff RTL Synthesis HDL netlist logic optimization netlist Library/ module generators physical design layout manual design a b s q 0 1 d clk a b s q 0 1 d ASIC signoff Use static analysis techniques to verify: (1) functionality: formal equivalence- checking techniques (2) timing: static timing analysis Courtesy K. Keutzer, UCB

10. ECE 260B – CSE 241A Verification 10http://vlsicad.ucsd.edu Problem: RTL to RTL Verification  After verification RTL may still be modified for: l performance l power l area l testability  Need to verify that new RTL is correct Courtesy K. Keutzer, UCB

11. ECE 260B – CSE 241A Verification 11http://vlsicad.ucsd.edu Problem: RTL to Gates Verification  Verify the gate level implementation is consistent with the RTL level design  Errors may have occurred due to l Logic synthesis l Manual intervention HDL DesignImplementation Courtesy K. Keutzer, UCB

12. ECE 260B – CSE 241A Verification 12http://vlsicad.ucsd.edu Problem: Gates to Gates Verification  Verify the modified gate level implementation is consistent with the RTL level design  Errors may have occurred due to l Incorrect logic synthesis or module generation l Test insertion l Scan chain reordering l Clock tree synthesis l Post layout “tweaks” NetlistImplementation Courtesy K. Keutzer, UCB

13. ECE 260B – CSE 241A Verification 13http://vlsicad.ucsd.edu Problem: Layout to Gates Verification (LVS)  Verify that physical implementation is consistent with the above gate and RTL level design representations  Errors may have occurred due to l Errors in physical design tools l Manual changes in layout  Verification is primarily graphical or ``topological’’: gate identification from transistor networks, subgraph isomorphism netlistphysical layout Courtesy K. Keutzer, UCB

14. ECE 260B – CSE 241A Verification 14http://vlsicad.ucsd.edu Solving Layout to Gates Verification (LVS)  Extract gate level models from physical level  Graphically compare extracted model against gate- level schematic (layout versus schematic)  Flag any discrepancies netlistphysical layout Courtesy K. Keutzer, UCB

15. ECE 260B – CSE 241A Verification 15http://vlsicad.ucsd.edu The Verification Gap  Verification determines whether a design satisfies its requirements (a.k.a. its specification): l Does it satisfy its functional requirements? l Does it satisfy its speed requirements? l etc.  There is a growing gap between l the amount of verification that is desired, and l the amount that can be done  The gap is caused by l Inadequate coverage with simulation l Approximate models (wire delays, for example) l etc. Coutesy, A. Nardi, UCB

16. ECE 260B – CSE 241A Verification 16http://vlsicad.ucsd.edu Formal Verification Reduces the Gap  Formal verification can give complete coverage l Mathematical techniques used to analyze all possible simulation vectors, without simulating them one by one l No test cases needed  But formal verification cannot replace simulation l Current technology only effective for certain verification subtasks  Using formal verification effectively requires understanding its strengths and weaknesses Coutesy, A. Nardi, UCB

17. ECE 260B – CSE 241A Verification 17http://vlsicad.ucsd.edu Formal Verification vs Informal Verification Formal Verification  Complete coverage  Effectively exhaustive simulation  Cover all possible sequences of inputs  Check all corner cases  No test vectors are needed Informal Verification  Incomplete coverage  Limited amount of simulation  Spot check a limited number of input seq’s  Some (many) corner cases not checked  Designer provides test vectors (with help from tools) Coutesy, A. Nardi, UCB

18. ECE 260B – CSE 241A Verification 18http://vlsicad.ucsd.edu Complete Coverage Example  For these two circuits: f = ab(c+d) = abc + abd = g l So the circuits are equivalent for all inputs  Such a proof can be found automatically l No simulation needed a b c a b d g = abc+abd a b c d f = ab(c+d) Coutesy, A. Nardi, UCB

19. ECE 260B – CSE 241A Verification 19http://vlsicad.ucsd.edu Using Formal Verification  No test vectors  Equivalent to exhaustive simulation over all possible sequences of vectors (complete coverage) Formal Verification Tool “Correct” or a Counter-Example: Requirements Design Coutesy, A. Nardi, UCB

20. ECE 260B – CSE 241A Verification 20http://vlsicad.ucsd.edu Types of Specifications Requirements design should satisfy Requirements are precise: a must for formal verification Is one design equivalent to another? Design has certain good properties? Informal Specification EquivalenceProperties Formal Coutesy, A. Nardi, UCB

21. ECE 260B – CSE 241A Verification 21http://vlsicad.ucsd.edu Formal vs Informal Specifications  Formal requirement l No ambiguity l Mathematically precise l Might be executable  A specification can have both formal and informal requirements l Processor multiplies integers correctly (formal) l Lossy image compression does not look too bad (informal) Coutesy, A. Nardi, UCB

22. ECE 260B – CSE 241A Verification 22http://vlsicad.ucsd.edu Types of Formal Verification Different comb. equiv. methods give different market opportunities; must be understood for FV strategy Property Checking Formal Verification SequentialCombinational Equivalence Checking Capacity Distinction between property checking and equiv. checking is becoming common knowledge Similarity Required Coutesy, A. Nardi, UCB

23. ECE 260B – CSE 241A Verification 23http://vlsicad.ucsd.edu Equiv. Checking vs Property Checking  Equivalence checking l Is one design equivalent to another? l One of the designs (the specification) is trusted l In practice, most useful at low levels of abstraction  Property checking l Does the design have a given desirable property? l Properties are relatively small and easy to state, e.g. -Each packet sent is eventually acknowledged -Never more than one bus master l Do not need complete set of properties -Set of properties can evolve during design process l Most useful at high levels of abstraction -Finds bugs early Coutesy, A. Nardi, UCB

24. ECE 260B – CSE 241A Verification 24http://vlsicad.ucsd.edu Types of Equivalence Checking Layout Trans. netlist Gate level netlist RTL netlist Behavioral desc. Layout Trans. netlist Gate level netlist RTL netlist Behavioral desc.  Structure of the designs is important l If the designs have similar structure, l then equivalence checking is much easier  More structural similarity at low levels of abstraction Coutesy, A. Nardi, UCB

25. ECE 260B – CSE 241A Verification 25http://vlsicad.ucsd.edu Degree of Similarity: State Encoding  Two designs have the same state encoding if l Same number of registers l Corresponding registers always hold the equal values  Register correspondence a.k.a. register mapping l Designs have the same state encoding if and only if l there exists a register mapping  Greatly simplifies verification l If same state encoding, l then combinational equivalence algorithms can be used Coutesy, A. Nardi, UCB

26. ECE 260B – CSE 241A Verification 26http://vlsicad.ucsd.edu Producing the Register Mapping  By hand l Time consuming l Error prone l Can cause misleading verification results  Side-effect of methodology l Mapping maintained as part of design database  Automatically produced by the verification tool l Minimizes manual effort l Depends on heuristics Coutesy, A. Nardi, UCB

27. ECE 260B – CSE 241A Verification 27http://vlsicad.ucsd.edu Degree of Similarity: Combinational Nets  Corresponding nets within a combinational block l Corresponding nets compute equivalent functions  With more corresponding nets l Similar circuit structure l Easier combinational verification  Strong similarity l If each and every net has a corresponding net in the other circuit, l then structural matching algorithms can be used Coutesy, A. Nardi, UCB

28. ECE 260B – CSE 241A Verification 28http://vlsicad.ucsd.edu Degree of Similarity: Summary  Different state encodings l General sequential equivalence problem l Expert user, or only works for small designs  Same state encoding, but combinational blocks have different structure l IBM’s BoolsEye l Compass’ VFormal  Same state encoding and similar combinational structure l Chrysalis (but weak when register mapping is not provided by user)  Nearly identical structure: structural matching l Compare gate level netlists (PBS, Chrysalis) l Checking layout vs schematic (LVS) Weak Similarity Strong Similarity Coutesy, A. Nardi, UCB

29. ECE 260B – CSE 241A Verification 29http://vlsicad.ucsd.edu Capacity of a Comb. Equiv. Checker  Matching pairs of fanin cones can be verified separately l How often a gate is processed is equal to the number of registers it affects l Unlike synthesis, natural subproblems arise without manual partitioning l “Does it handle the same size blocks as synthesis?” is the wrong question l “Is it robust for my pairs of fanin cones?” is a better question  Structural matching is easier l Blocks split further (automatically) l Each gate processed just once Coutesy, A. Nardi, UCB

30. ECE 260B – CSE 241A Verification 30http://vlsicad.ucsd.edu User Needs  Gate vs Gate (structural) l Post-synthesis step: verify netlist updates (scan insertion, buffers, etc) l ASIC designer, ASSPs, ASIC vendor, Design Factories l Limited debugging support required  Gate vs Gate (nonstructural) l Manual optimization following synthesis l High performance, high volume design (microProc, fabless, ASSPs) l Requires good debugging support l No current robust commercial offering Coutesy, A. Nardi, UCB

31. ECE 260B – CSE 241A Verification 31http://vlsicad.ucsd.edu User Needs (cont.)  RTL vs Gate l Simulation mostly at RTL level, reduce simulation at gate level l ASIC designers, ASSPs, Design Factories and future DSM signoff l Sophisticated debugging support required (source level) l Methodology support required -Hierarchy and black boxes required for IP -Synthesis/simulation mismatch due to Synopsys don’t cares l Capacity and robustness are critical l No dominant player yet Coutesy, A. Nardi, UCB

32. ECE 260B – CSE 241A Verification 32http://vlsicad.ucsd.edu User Needs (cont.)  RTL vs RTL l IP resurrection and multiple revisions l Similar to RTL vs gate  Gate or RTL vs Transistor l Processor companies, library development l Key issue is robustness of automatic transistor extraction Coutesy, A. Nardi, UCB

33. ECE 260B – CSE 241A Verification 33http://vlsicad.ucsd.edu Techniques  Random simulation l Finds many unequal nets (but not all)  OBDDs l Construct OBDDs representing all or part of a combinational block l Canonical form: cheap to compare l Potentially expensive to build  Structural matching l Specialized techniques to quickly verify identical structure  Decomposition points l Find matching internal nets, if they exist Coutesy, A. Nardi, UCB

34. ECE 260B – CSE 241A Verification 34http://vlsicad.ucsd.edu Techniques (cont.)  Pattern matching l Transform circuits to increase similarity l Examples: remove inverter pairs and buffers, use de Morgan’s laws  Case splitting l Exhaustively consider all combinations of inputs to a block l A given case may leave some inputs undetermined l Therefore, many fewer than 2 # inputs cases may be sufficient Coutesy, A. Nardi, UCB

35. ECE 260B – CSE 241A Verification 35http://vlsicad.ucsd.edu Equivalence Checking: Research  Early academic research into tautology checking l A formula is a tautology if it is always true l Equivalence checking: f equals g when (f = g) is a tautology l Used case splitting l Ignored structural similarity often found in real world  OBDDs [Bryant 1986] l Big improvement for tautology checking [Malik et. al 1988, Fujita et. al 1988, Coudert and Madre et. al 1989] l Still did not use structural similarity  Using structural similarity l Combine with ATPG methods [Brand 1993, Kunz 1993] l Continuing research on combining OBDDs with use of structural similarity Coutesy, A. Nardi, UCB

36. ECE 260B – CSE 241A Verification 36http://vlsicad.ucsd.edu Equivalence Checking: Tools  Internal tools from processor companies l IBM (sold as BoolsEye), Motorola, DEC, Intel, BULL, etc.  VFormal from Compass l OBDD-based, licensed from BULL  CheckOff-E from Abstract Hardware l OBDD-based sequential equivalence checker  Design VERIFYer from Chrysalis l No OBDDs, but “symbolic logic” is only a slight extension of the netlist data structures used in synthesis Coutesy, A. Nardi, UCB

37. ECE 260B – CSE 241A Verification 37http://vlsicad.ucsd.edu Equivalence Checking Summary  Routinely verify complex (>1M gate) integrated circuit designs  Commercial (e.g., Synopsys, Cadence (Verplex)) and proprietary (e.g., IBM) solutions exist  Static sign-off methodology more widely used  Successful equivalence checkers orchestrate several different approaches l syntactic equivalence l automatic test pattern generation-like approaches l BDD-based techniques l pattern-reduction methods  Open issues l retimed circuits l circuits with differing state assignments Courtesy K. Keutzer, UCB

38. ECE 260B – CSE 241A Verification 38http://vlsicad.ucsd.edu Physical Verification

39. ECE 260B – CSE 241A Verification 39http://vlsicad.ucsd.edu Overview  What is Physical Verification (PV)?  General PV topics l Design Rule Check (DRC) l Logical Versus Schematic (LVS) l Verification Algorithms -Flat and Hierarchical  Approaches l DRC -Place and Route, Flat and Hierarchical l LVS -Place and Route, Flat and Hierarchical Courtesy Cadence Design Systems, Inc.

40. ECE 260B – CSE 241A Verification 40http://vlsicad.ucsd.edu What is Design Rule Checking?  Verification that layout geometry is legal l obeys set of design rules l minimum widths and spacings l extensions, overlaps l circuit-dependent rules  Goal l verify that all rules are met l highlight places that rules fail and why l use minimum CPU time, memory l integrated DRC + layout editor -use existing data structures -check incrementally A B S min = 3 if V AB < 2.5V, S min = 4 otherwise Slide courtesy, H. Walker, TAMU

41. ECE 260B – CSE 241A Verification 41http://vlsicad.ucsd.edu Why Design Rule Checking?  Manufacturing resolution limits l can only pattern line widths and spacings above W min and S min l limits of photolithography, optics, etc.  Manufacturing alignment limits l overlay registration varies slightly l repeatability of mechanics, sensors  Manufacturing disturbances l line over/under etching l furnace temperature variations l particles  Layout design rules l obey them to get high manufacturing yield l a compromise between yield and density l rules are local in nature vs. Slide courtesy, H. Walker, TAMU

42. ECE 260B – CSE 241A Verification 42http://vlsicad.ucsd.edu Geometry Representation  Polygon l rectangles as special case l most natural representation l simple specification of most design rules l requires good polygon package  Raster l at design rule resolution l memory hog  Tile l corner-stitched rectangles, trapezoids l good for incremental analysis l local connections already stored  Edge l requires connectivity information l minimal memory 001000 011101 001000 Slide courtesy, H. Walker, TAMU

43. ECE 260B – CSE 241A Verification 43http://vlsicad.ucsd.edu Polygon DRC  Design rules in terms of boolean operations l Met-Met spacing > 3 lambda -MetI = inflate(Met, 1.5) -Error = MetI MetI  Issues l inflation of oblique angles l robustness of polygon package l speed -O(nm) operation for n and m-edge polygons l memory -many auxiliary structures for each edge -2 floats, 5 points in DMW polygon package l must merge electrically connected polygons l must restrict checks to neighboring polygons -avoid O(n 2 ) checks for n polygons A B A BA - BA B Slide courtesy, H. Walker, TAMU

44. ECE 260B – CSE 241A Verification 44http://vlsicad.ucsd.edu Polygon Operations  Find edge intersections l O(nm) time for n and m edge polygons l use neighborhood check to reduce average to (nlogn) l split edges at intersections  Walk the edges l keeping to edges that are on outside of result polygon l use wrap/winding number to compute inside/outside -edge crossings of horizontal ray +1+1 sum = +1 => inside worst-case Slide courtesy, H. Walker, TAMU

45. ECE 260B – CSE 241A Verification 45http://vlsicad.ucsd.edu Neighborhood Checking  Design rules are local - only check neighborhood l objects spread evenly across chip -number of neighbors roughly constant  Bin sorting l divide chip into c x c bins l bin points to all objects that intersect it l O(1) time to check nearby bins for objects  Quad tree l search tree - log(n) time to find neighbors  Scan line l only hold objects within design rule of scan line l cutline on n-object chip hits ~sqrt(n) objects l n*log(n) time to scan all objects  Corner-stitching l inherent neighborhood relationships Slide courtesy, H. Walker, TAMU

46. ECE 260B – CSE 241A Verification 46http://vlsicad.ucsd.edu Raster DRC  Scan window over raster l d x d for maximum design rule of d units l table lookup of d x d window -window passes/fails -precompute tables l one bit per layer -layer combinations via bit operations -very fast  Issues l fine grid design rules => large raster -I/O time, memory consumption -rasterization time -use scan line to select polygons to rasterize l large d => large tables l limited to Manhattan geometry l works best on simple MOSIS design rules space 2 ok Slide courtesy, H. Walker, TAMU

47. ECE 260B – CSE 241A Verification 47http://vlsicad.ucsd.edu Line Scanning Algorithm O(nlgn) runtime Many applications, e.g., edge based DRC  Input: layout features represented in non-vertical edges  Output: geometric Boolean operation results 1.Sort the edge endpoints in x-coordinates into Q 2.While(Q not empty) { 3. Pop up edge endpoints E with smallest x-coordinates 4. Insert E into active edge set A 5. Merge sort A in y-coordinates 6. Remove an edge e from A if both endpoints of e are in A 7. Compute possible crosspoints, merge sort to Q 8. Perform Boolean operation 9.} 00 10 11 01 00

48. ECE 260B – CSE 241A Verification 48http://vlsicad.ucsd.edu Design Rule Checks (DRCs) Goals:  Manufacturability  Yield Analysis Inputs:  Foundry l Rules  Design data l Mask data, Layer information Typical checks performed: For Manufacturing  Width, Spacing, Minimum Area, Enclosed Area, Overhang, etc. For Yield  Antenna, Electromigration, Latch- up, Electrostatic Discharge, Density DRC Violations Report Violations Markers Rules Deck Design (Layout) Courtesy Cadence Design Systems, Inc.

49. ECE 260B – CSE 241A Verification 49http://vlsicad.ucsd.edu Design Rule Waivers  Well tested special structures l Memory macros  Special permissions with the cost of reduced yield l Antenna rules l Density rules l EM rules Courtesy Cadence Design Systems, Inc.

50. ECE 260B – CSE 241A Verification 50http://vlsicad.ucsd.edu Layout Versus Schematic (LVS) Goals:  Functionality Analysis Inputs:  Foundary or Library Vendor l Library Spice Netlist  Design data l Mask data, Logic Netlist Typical checks performed:  Connectivity Recognition  Device Recognition LVS Violations Report Violations Markers Spice Netlist Design (Layout &Netlist) Courtesy Cadence Design Systems, Inc.

51. ECE 260B – CSE 241A Verification 51http://vlsicad.ucsd.edu Design Transistors:Design Layout: Analysis Process Steps:Design Netlist: I1I3 I2I4 IN1 O1 Net2Net1Net3 IN1O1 From Gates to Transistors Primary I/Os Identified Connectivity Traced Device Recognition Net1 Net2 Net3 BA VDD GND BA VDD GND 2/1 1/1 2/1 1/1 I1 I2 I3 I4 Net3 Net1 Net2 Courtesy Cadence Design Systems, Inc.

52. ECE 260B – CSE 241A Verification 52http://vlsicad.ucsd.edu Flat Verification Verification Performed on a Flat Database T1 C1C2C1 H2H1 C2C1 H2 T1 H1 All Levels Flattened to a Single Level Schematic Netlist Layout Netlist T1 C1C2C1 H2H1 C2C1 H2 T1 H1 T1 C1C2C1 H2H1 C2C1 H2 T1 H1 T1 C1C2C1 H2H1 C2C1 H2 T1 H1 T1 C1C2C1 H2H1 C2C1 H2 T1 H1 Courtesy Cadence Design Systems, Inc.

53. ECE 260B – CSE 241A Verification 53http://vlsicad.ucsd.edu Hierarchical Verification T1 C1C2C1 H2H1 C2C1 H2 T1 H1 Schematic Netlist Layout Netlist Check Cells Verified Cells not verified since C1 already checked Cells Verified Top Level Verified Skip T1 C1C2 H2H1 Cells Verified Courtesy Cadence Design Systems, Inc.

54. ECE 260B – CSE 241A Verification 54http://vlsicad.ucsd.edu Approaches  DRC l Place and Route Environment l Flat l Hierarchical  LVS l Place and Route Environment l Flat l Hierarchical Courtesy Cadence Design Systems, Inc.

55. ECE 260B – CSE 241A Verification 55http://vlsicad.ucsd.edu DRC: In Place and Route Advantages:  Fast  Small database  Problems can be debugged and fixed fast. Disadvantages:  Checking is only as accurate as the abstracts.  No checks at different hierarchy levels.  Connection to pins could have violations. Description: All cells are modeled with abstracts. No detailed layout is available. IO Pad modeled with abstracts Sub blocks modeled with abstracts Hard Macro modeled with abstracts Courtesy Cadence Design Systems, Inc.

56. ECE 260B – CSE 241A Verification 56http://vlsicad.ucsd.edu DRC: Flat Advantages:  Single run for entire chip, simple to setup  Has to be performed prior to every tape out  No modeling requirements Disadvantages:  Entire design completed  Long run times  Resource requirements  Harder to debug Description: All cells are flattened. All geometric shapes visible. No black boxes. IO Pad Flattening Sub blocks merged at the top Hard Macro Flattening Courtesy Cadence Design Systems, Inc.

57. ECE 260B – CSE 241A Verification 57http://vlsicad.ucsd.edu DRC: Hierarchical Advantages:  Start before entire chip completed  Smaller data size = shorter run times, simpler debugging, easier to fix  Early density, EM, wide metal checks and repair  Effects seen on timing, SI early when it can still be addressed Disadvantages:  Proper modeling of over the block and through the block routes  Full flat chip analysis is still required  Density checks may be inaccurate  Assumptions made at hierarchy boundaries Description:  Bottom-up checking starting at block/hard macro level  Blocks verified separately  Top level verified using black box models for sub-blocks Courtesy Cadence Design Systems, Inc.

58. ECE 260B – CSE 241A Verification 58http://vlsicad.ucsd.edu LVS: In Place and Route Advantages:  Fast  Small database  Problems can be debugged and fixed fast. Disadvantages:  Only connectivity check of the nets.  No checks at different hierarchy levels. Description: All cells are modeled with abstract. No cell layout and netlist available. IO Pad modeled with abstracts Sub blocks modeled with abstracts Hard Macro modeled with abstracts Courtesy Cadence Design Systems, Inc.

59. ECE 260B – CSE 241A Verification 59http://vlsicad.ucsd.edu LVS: Flat Advantages:  Simple setup, implementation  No modeling requirement  Run before all tape outs regardless Disadvantages:  Large data yielding long run times  Hard to debugging  Late in design cycle hard to accommodate changes Description:  Design flattened to one level.  Primary I/Os and supply I/Os labeled  Entire IC layout compared to transistor level schematic. Courtesy Cadence Design Systems, Inc.

60. ECE 260B – CSE 241A Verification 60http://vlsicad.ucsd.edu LVS: Hierarchical Advantages:  Reduced amount of data yielding faster run times  Easier to debug  Data maturity (incomplete block)  Fixing problems early in design easier  IP issues, verification reuse Disadvantages:  Full flat chip analysis still required  Modeling errors possible Description:  Bottom-up checking starting at block/hard macro level  Blocks verified separately  Top level verified w/black box models for sub-blocks  Connections to black boxes checked but not content Courtesy Cadence Design Systems, Inc.

61. ECE 260B – CSE 241A Verification 61http://vlsicad.ucsd.edu Hierarchical Filling Problem  Filling geometries are added only to master cells Two instances of a master cell Original layout features Flat fill solution Hierarchical fill solution  Each cell of the filled layout is a filled version of the corresponding original master cell

62. ECE 260B – CSE 241A Verification 62http://vlsicad.ucsd.edu Why Hierarchical Filling?  Hierarchy characteristics of custom and semi-custom design flows  Enables and faster verification of the filled layout  Decreases data volume for standard cell designs

63. ECE 260B – CSE 241A Verification 63http://vlsicad.ucsd.edu Difficulties of Hierarchical Filling  Density constraints for all instances of the master  Interactions / interferences at master cell boundaries  Always worse than flat solutions

64. ECE 260B – CSE 241A Verification 64http://vlsicad.ucsd.edu C1C1 CiCi C2C2 C2`C2` C1`C1` C1`C1` C2`C2` CiCi C2C2 C1C1 C i,1 C i,2 C1`C1` C2`C2` C2C2 C1C1 C1`C1` C2`C2` C i,1 C i,2  Create k copies of master cell C i  k   : hierarchical layout  flat layout C2`C2` C1`C1` C2`C2` C1`C1`  Link all contained master cell C` with the new copies of C i C1C1 C2C2  Randomly replace C i in any master cell with one of the new copies K Way Master Cell Splitting

65. ECE 260B – CSE 241A Verification 65http://vlsicad.ucsd.edu Hybrid Hierarchical / Flat Filling Purely hierarchical fill phase Flat fill `cleanup` phase Split-hierarchical phase features three instances of a master cell

66. ECE 260B – CSE 241A Verification 66http://vlsicad.ucsd.edu Physical Verification Summary  Tool modes l Hierarchical vs. Flat  Examining DRC and LVS errors l Design rule waivers  DRC and LVS approaches l Place and Route l Flat l Hierarchical  Dummy fill insertion l Flat l Hierarchical Courtesy Cadence Design Systems, Inc.

67. ECE 260B – CSE 241A Verification 67http://vlsicad.ucsd.edu Thanks