1. Carrier Mobility and Velocity Mobility - the ease at which a carrier (electron or hole) moves in a semiconductor Mobility - the ease at which a carrier (electron or hole) moves in a semiconductor –Symbol:  n for electrons and  p for holes Drift velocity – the speed at which a carrier moves in a crystal when an electric field is present Drift velocity – the speed at which a carrier moves in a crystal when an electric field is present –For electrons: v d =  n E –For holes: v d =  p E

2. H L W VaVa VaVa

3. Resistance

4. Resistivity and Conductivity Fundamental material properties Fundamental material properties

6. Resistivity n-type semiconductor p-type semiconductor

7. Drift Currents

8. Diffusion When there are changes in the concentration of electrons and/or holes along a piece of semiconductor When there are changes in the concentration of electrons and/or holes along a piece of semiconductor –the Coulombic repulsion of the carriers force the carriers to flow towards the region with a lower concentration.

9. Diffusion Currents

10. Relationship between Diffusivity and Mobility

11. Mobility vs. Dopant Concentration in Silicon http://www.ioffe.ru/SVA/NSM/Semicond/Si/electric.html#Hall

12. Wafer Characterization X-ray Diffraction X-ray Diffraction –Crystal Orientation Van der Pauw or Hall Measurements Van der Pauw or Hall Measurements –Resistivity –Mobility Four Point Probe Four Point Probe –Resisitivity Hot Point Probe Hot Point Probe –n or p-type material

13. Van der Pauw Four equidistant Ohmic contacts Four equidistant Ohmic contacts Contacts are small in area Contacts are small in area Current is injected across the diagonal Current is injected across the diagonal Voltage is measured across the other diagonal Voltage is measured across the other diagonal Top view of Van der Pauw sample http://www.eeel.nist.gov/812/meas.htm#geom

14. Calculation Resistance is determined with and without a magnetic field applied perpendicular to the sample. Resistance is determined with and without a magnetic field applied perpendicular to the sample. F is a correction factor that takes into account the geometric shape of the sample.

15. Hall Measurement See http://www.eeel.nist.gov/812/hall.html for a more complete explanation See http://www.eeel.nist.gov/812/hall.html for a more complete explanationhttp://www.eeel.nist.gov/812/hall.html http://www.sp.phy.cam.ac.uk/SPWeb/research/QHE.html

16. Calculation Measurement of resistance is made while a magnetic field is applied perpendicular to the surface of the Hall sample. Measurement of resistance is made while a magnetic field is applied perpendicular to the surface of the Hall sample. –The force applied causes a build-up of carriers along the sidewall of the sample  The magnitude of this buildup is also a function of the mobility of the carriers where A is the cross-sectional area.

17. Four Point Probe Probe tips must make an Ohmic contact Probe tips must make an Ohmic contact –Useful for Si –Not most compound semiconductors

18. Hot Point Probe Simple method to determine whether material is n-type or p-type Simple method to determine whether material is n-type or p-type –Note that the sign of the Hall voltage, V H, and on  R 13,24 in the Van der Pauw measurement also provide information on doping.

19. Visual Information on Crystal Orientation and Doping Used on wafers that are less than 200 mm in diameter (8 inches)

20. Key Inventions Three discoveries made integrated circuits possible: Three discoveries made integrated circuits possible: –Invention of the transistor (1949 by Brattain, Bardeen, and Schockley; Nobel prize 1972) –Development of planar transistor technology (1959 by Bob Noyce and Jean Hoerni; Noyce was a founder of Intel) –Invention of integrated circuit (1959 by Kilby; Nobel prize 2000)

21. The First Transistor The first transistor, a point contact pnp Ge device, was invented in 1947 by John Bardeen, Walter Brattain, and William Shockley. They received the Nobel Prize in physics in 1956. The first transistor, a point contact pnp Ge device, was invented in 1947 by John Bardeen, Walter Brattain, and William Shockley. They received the Nobel Prize in physics in 1956.

22. The first integrated circuit The first integrated circuit was invented by Jack Kilby of TI. He received the Nobel Prize in 2000. The first integrated circuit was invented by Jack Kilby of TI. He received the Nobel Prize in 2000.

23. Levels of Integrated Circuits Small Scale Integration (SSI) Small Scale Integration (SSI)  1-10 transistors Medium Scale Integration (MSI) Medium Scale Integration (MSI)  up to 100 transistors Large Scale Integration (LSI) Large Scale Integration (LSI)  up to 10,000 transistors Very Large Scale Integration (VLSI) Very Large Scale Integration (VLSI)  millions of transistors Ultra Large Scale Integration Ultra Large Scale Integration Wafer Scale Integration Wafer Scale Integration System on a Chip (SOC) System on a Chip (SOC) 3D IC 3D IC

24. Increase in Complexity of Chips

25. Moore’s Law Gordon Moore observed (1965) that the number of transistors on a Si chip was doubling every year. Later, revised this to every 18 months. Gordon Moore observed (1965) that the number of transistors on a Si chip was doubling every year. Later, revised this to every 18 months. –This cannot continue forever; when components reach size of atoms, the physics changes. –Currently, there is no known solution.

27. Historical Trends of Minimum Feature Size Minimum Feature Size: 13% reduction each year; recently closer to 10%.

28. Projections from 1997 Roadmap The fundamental assumption is that Si will be the material of choice and that Moore’s law will apply until 2012 The fundamental assumption is that Si will be the material of choice and that Moore’s law will apply until 2012

29. Scaling as a Function of Cycle Time S is the minimum feature size T is the cycle time CARR is the Compound Annual Reduction Rate On average, the minimum feature size decreases by 10-13%/year. Currently at 45 or 32 nm node

30. Where are we today?

34. Semiconductor Trends Overall chip size has been increasing by 16%/year over past 35 years Overall chip size has been increasing by 16%/year over past 35 years –Recently 6.3%/year for microprocessors and 12%/year for DRAM –Major limitation is the number of pads that can be placed on the chip to get signals in and out Trends are now projected by the SIA national Technology Roadmap for Semiconductors Trends are now projected by the SIA national Technology Roadmap for Semiconductors  Current version is called International Technology Roadmap for Semiconductors International Technology Roadmap for SemiconductorsInternational Technology Roadmap for Semiconductors

36. Cost of Designing a Chip The cost of designing a chip has increased with the complexity of the chip. The cost of designing a chip has increased with the complexity of the chip. –Initially, the cost seemed to follows Moore’s law—the cost doubled every time the complexity doubled. –The controlling factor was the development of CAD and modeling software.

37. Cleanrooms Federal Standard TC 209 ISO 1 2 13 104 1005 1,0006 10,0007 100,0008 9

38. First Line of Protection: Bunny Suits www.intel.com