1. Figure 10.1. A flip-flop with an enable input. D Q Q Q R Clock E 0 1

2. Figure 10.2. Code for a D flip-flop with enable. module rege (R, Clock, Resetn, E, Q); input R, Clock, Resetn, E; output Q; reg Q; always @(posedge Clock or negedge Resetn) if (Resetn == 0) Q <= 0; else if (E) Q <= R; endmodule

3. Figure 10.3. An n-bit register with an enable input. module regne (R, Clock, Resetn, E, Q); parameter n = 8; input [n-1:0] R; input Clock, Resetn, E; output [n-1:0] Q; reg [n-1:0] Q; always @(posedge Clock or negedge Resetn) if (Resetn == 0) Q <= 0; else if (E) Q <= R; endmodule

4. Figure 10.4. A shift register with parallel-load and enable control inputs.

5. Figure 10.5. A right-to-left shift register with an enable input. module shiftlne (R, L, E, w, Clock, Q); parameter n = 4; input [n-1:0] R; input L, E, w, Clock; output [n-1:0] Q; reg [n-1:0] Q; integer k; always @(posedge Clock) begin if (L) Q <= R; else if (E) begin Q[0] <= w; for (k = 1; k < n; k = k+1) Q[k] <= Q[k-1]; end endmodule

6. Figure 10.6. An SRAM cell. Sel Data

7. Figure 10.7. A 2 x 2 array of SRAM cells. Sel 1 0 Data 0 1

8. Figure 10.8. A 2 m x n SRAM block. Sel 2 1 0 2 m 1” Read Write d 0 d n1– d n2– q 0 q n1– q n2– m -to-2 m decoder Address a 0 a 1 a m1– Data outputs Data inputs

9. Figure 10.9. Pseudo-code for the bit counter. B=0; while A  0 do if a 0 =1 then B=B+1 ; end if; Right-shift A ; end while;

10. Figure 10.10. ASM chart for the pseudo-code in Figure 10.9. Please see “portrait orientation” PowerPoint file for Chapter 10

11. Figure 10.11. Datapath for the ASM chart in Figure 10.10.

12. Figure 10.12. ASM chart for the bit counter datapath circuit.

13. Figure 10.13. Verilog code for the bit-counting circuit. Please see “portrait orientation” PowerPoint file for Chapter 10

14. Figure 10.14. Simulation results for the bit-counting circuit.

15. Figure 10.15. An algorithm for multiplication. (a)Manualmethod P=0 ; for i=0 to n1 do if b i =1 then P=P+A ; endif; Left-shift A ; endfor; (b)Pseudo-code Multiplicand1 1 Product Multiplier1 0 0 1 1 1 1101 1011 0000 1011 01001111  Binary 13 11  13 143 Decimal –

16. Figure 10.16. ASM chart for the multiplier. Please see “portrait orientation” PowerPoint file for Chapter 10

17. Figure 10.17. Datapath circuit for the multiplier. Please see “portrait orientation” PowerPoint file for Chapter 10

18. Figure 10.18. ASM chart for the multiplier control circuit. Please see “portrait orientation” PowerPoint file for Chapter 10

19. Figure 10.19. Verilog code for the multiplier circuit. Please see “portrait orientation” PowerPoint file for Chapter 10

20. Figure 10.20. Simulation results for the multiplier circuit.

21. Figure 10.21. An algorithm for division. R=0 ; for i=0 to n1 do Left-shift R  A ; ifR  B then q i =1 ; R=RB ; else q i =0 ; endif; endfor; (c) Pseudo-code 9140 9 50 45 5 15 100 10 011001001 00001111 1001 001 01 10000 1001 1110 1001 101 Q A B R (a) An example using decimal numbers (b) Using binary numbers – –

22. Figure 10.22. ASM chart for the divider. Please see “portrait orientation” PowerPoint file for Chapter 10

23. Figure 10.23. Datapath circuit for the divider.

24. Figure 10.24. ASM chart for the divider control circuit. Please see “portrait orientation” PowerPoint file for Chapter 10

25. Figure 10.25. An example of division using n = 8 clock cycles. Load A, B0 0 0 1 0 0 1 1 0 1 2 3 1 0 0 0 0 0 4 5 600 7 1 0 0 0 1 1 0 0 Clock cycle 00 8 0 A/Q 0 1 1 0 1 1 0 0 0 0 0 0 0 0 00 00 1 0 0 0 0 0 0 0 0 0 0 0 0 0 01 11 0 0 0 0 0 0 1 1 1 00 0 01111 rr 0 R 0 0 0 0 0 0 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 1 1 1 0 0 10 01 0 0 0 1 0 0 1 0 0 0 0 0 0 0 00 11 0 1 0 0 0 1 1 0 0 00 0 01010 0 0 0 0 0 0 0 0 0 0 100011001001AB Shift left Subtract, Q 0 1  Shift left, Q 0 0 , Q 0 0 , Q 0 0  Subtract, Q 0 1 , Q 0 1 , Q 0 1  Shift left, Q 0 0 

26. Figure 10.26. ASM chart for the enhanced divider control circuit. Please see “portrait orientation” PowerPoint file for Chapter 10

27. Figure 10.27. Datapath circuit for the enhanced divider. Please see “portrait orientation” PowerPoint file for Chapter 10

28. Figure 10.28. Verilog code for the divider circuit. Please see “portrait orientation” PowerPoint file for Chapter 10

29. Figure 10.29. Simulation results for the divider circuit.

30. Figure 10.30. An algorithm for finding the mean of k numbers. Please see “portrait orientation” PowerPoint file for Chapter 10

31. Figure 10.31. Datapath circuit for the mean operation. Please see “portrait orientation” PowerPoint file for Chapter 10

32. Figure 10.32. ASM chart for the mean operation control circuit. Please see “portrait orientation” PowerPoint file for Chapter 10

33. Figure 10.33. Schematic of the mean circuit with an SRAM block.

34. Figure 10.34. Simulation results for the mean circuit using SRAM.

35. Figure 10.35. Pseudo-code for the sort operation. for i=0 to k2 do A=R i ; for j=i+1 to k1 do B=R j ; if B<A then R i =B ; R j =A ; A=R i ; end if; end for; – –

36. Figure 10.36. ASM chart for the sort operation. Please see “portrait orientation” PowerPoint file for Chapter 10

37. Figure 10.37. A part of the datapath circuit for the sort operation.

38. Figure 10.38. A part of the datapath circuit for the sort operation.

39. Figure 10.39. ASM chart for the control circuit. Please see “portrait orientation” PowerPoint file for Chapter 10

40. Figure 10.40. Verilog code for the sorting circuit. Please see “portrait orientation” PowerPoint file for Chapter 10

41. Figure 10.41. Simulation results for the sort operation. Please see “portrait orientation” PowerPoint file for Chapter 10

42. Figure 10.42. Using tri-state buffers in the datapath circuit.

43. Figure 10.43. Clock enable circuit. D Q Q Data Clock E

44. Figure 10.44. An H tree clock distribution network. Clock ff

45. Figure 10.45. A flip-flop in an integrated circuit.

46. Figure 10.46. Flip-flop timing in a chip.

47. Figure 10.47. Asynchronous inputs. D Q Q Data Clock (asynchronous) D Q Q Data (synchronous)

48. Figure 10.48. Switch debouncing circuit. Data S R V DD R V R (a) Single-pole single-throw switch Data V DD R (b) Single-pole double-throw switch with a basic SR latch

49. Figure P10.1. Pseudo-code for integer division. Q=0 ; R=A ; while ((RB)>0) do R=RB ; Q=Q +1 ; end while; – –

50. Figure P10.2. The 555 programmable timer chip. 5 V R b R a 555 Timer 8 7 6 51 2 3 4 C 1 0.01  F Clock (output)