1. 11 Workshop on Information Technology March 2005 - Shanghaï CONFIDENTIAL Architectures & Digital IC design

2. 2 CONFIDENTIAL Workshop on Information Technology March 2005 - Shanghaï Advanced Design Departements (Architecture Design Laboratory of CEA) Jean-René LEQUEPEYS lequepeys@chartreuse.cea.fr - 33 (0)4 38 78 37 49 Grenoble Thierry COLLETTE Thierry.collette@cea.fr - 33 (0)1 69 08 65 25 Paris ORGANIZATION

3. 3 CONFIDENTIAL Workshop on Information Technology March 2005 - Shanghaï  Integrated circuit design (ASIC) : analog, mixed and RF  Parameter extraction of technologies – Component modeling  Architecture design : parallel and reconfigurable  Integrated circuit design (ASIC) : analog, mixed and RF  Parameter extraction of technologies – Component modeling  Architecture design : parallel and reconfigurable  Design of Integrated Circuits for CEA projects (40 %)  ASIC & IP design for partners (60%)  Design of ASIC and ASIP on emerging technologies (advanced CMOS, MEMs…)  Validation of new concepts (heterogeneous design, advanced architectures).Patents on architecture, schemes, topologies  Applications fields : smart card, telecom, automotive, imagers, biochips, multimedia…  Design of Integrated Circuits for CEA projects (40 %)  ASIC & IP design for partners (60%)  Design of ASIC and ASIP on emerging technologies (advanced CMOS, MEMs…)  Validation of new concepts (heterogeneous design, advanced architectures).Patents on architecture, schemes, topologies  Applications fields : smart card, telecom, automotive, imagers, biochips, multimedia… ASIC Design Activities

4. 4 CONFIDENTIAL Workshop on Information Technology March 2005 - Shanghaï  Staff. 90 Full Time CEA Designers. + 29 PhD & Postdocs. + Students  About 15-20 Design per year  R&D of advanced design methodology  More than 700 Masks design per year (sensors, actuators, detectors, etc.)  Staff. 90 Full Time CEA Designers. + 29 PhD & Postdocs. + Students  About 15-20 Design per year  R&D of advanced design methodology  More than 700 Masks design per year (sensors, actuators, detectors, etc.) Design Activities

5. 5 CONFIDENTIAL Workshop on Information Technology March 2005 - Shanghaï CEA PhDs, Post-docs 2001200220032004 Growth of Design Activities 0 20 40 50 60 80 100 1234 CEA, PhDs, Post-docs

6. 6 CONFIDENTIAL Workshop on Information Technology March 2005 - Shanghaï Digital Architectures Reconfigurable computing Test and Reliability Design Activities organization Layout/Mask Ad. Techno Energy and Power mngt Imaging systems & Biochips Processor and multi-processor Architectures RF architecture & circuit

7. 7 CONFIDENTIAL Workshop on Information Technology March 2005 - Shanghaï Industrials partners  THALES, EADS  STMicroelectronics, INFINEON, PHILIPS, ATMEL  BICRON ST GOBAIN  NOKIA, MOTOROLA, PHILIPS  SOFRADIR, TRIXEL, ULIS  ALCATEL, SIEMENS  SIEMENS TRANSPORTATION SYSTEM  GEMPLUS Industrials partners  THALES, EADS  STMicroelectronics, INFINEON, PHILIPS, ATMEL  BICRON ST GOBAIN  NOKIA, MOTOROLA, PHILIPS  SOFRADIR, TRIXEL, ULIS  ALCATEL, SIEMENS  SIEMENS TRANSPORTATION SYSTEM  GEMPLUS Design Activities : Main Partners Academic / Institutes  CSEM  INPG/TIMA  IMEC  IMST  EPFL  IMEP  ESE  ESIEE  INRIA  … Academic / Institutes  CSEM  INPG/TIMA  IMEC  IMST  EPFL  IMEP  ESE  ESIEE  INRIA  …

8. 8 CONFIDENTIAL Workshop on Information Technology March 2005 - Shanghaï  ASIC Design. Standard Cells (Digital & Mixed ICs). Full Custom (Analog & Mixed ICs)  Addressed technologies ATMEL CMOS 0.35 µm, CMOS 0.5 µm STMICROELECTRONICSCMOS 0.09 µm, CMOS 0.13 µm, CMOS 0.18 µm, CMOS 0.25 µm, BICMOS6 0.35 µm, BICMOS7 0.25µm CMOS/SOI 0,13 µm AMSCMOS 0.35 µm, 0,8µm AMIBCD CMOS 0.7 µm MOTOROLA BCD 0.25 µm  ASIC Design. Standard Cells (Digital & Mixed ICs). Full Custom (Analog & Mixed ICs)  Addressed technologies ATMEL CMOS 0.35 µm, CMOS 0.5 µm STMICROELECTRONICSCMOS 0.09 µm, CMOS 0.13 µm, CMOS 0.18 µm, CMOS 0.25 µm, BICMOS6 0.35 µm, BICMOS7 0.25µm CMOS/SOI 0,13 µm AMSCMOS 0.35 µm, 0,8µm AMIBCD CMOS 0.7 µm MOTOROLA BCD 0.25 µm Design : Technology addressed today

9. 9 CONFIDENTIAL Workshop on Information Technology March 2005 - Shanghaï Design Activities - EDA Tools & Equipments  CAD for ICs design CADENCE (Analog/Digital/RF) MENTOR GRAPHICS ( Analog/Digital/RF ) SYNOPSYS (Digital IC's) AGILENT (RF IC's)  Modeling software's : MATLAB/SIMULINK, SystemC, ARM9xx and PowerPC…  Test and characterization on wafers and encapsulated circuits  Equipment for parameters extraction  CAD for ICs design CADENCE (Analog/Digital/RF) MENTOR GRAPHICS ( Analog/Digital/RF ) SYNOPSYS (Digital IC's) AGILENT (RF IC's)  Modeling software's : MATLAB/SIMULINK, SystemC, ARM9xx and PowerPC…  Test and characterization on wafers and encapsulated circuits  Equipment for parameters extraction

10. 10 CONFIDENTIAL Workshop on Information Technology March 2005 - Shanghaï  RF test and characterization  Noise characterization  Parameters extraction  Noise characterization  Parameters extraction  On wafer test and characterization Test and characterization  Embedded reliability

11. 11 CONFIDENTIAL Workshop on Information Technology March 2005 - Shanghaï Research domains Digital Architectures GALS Architectures Telecom and multimedia applications Low-power Reconfigurable architectures Network On Chip Design methodology Prototyping IC Application demonstrators Parallel architectures Mastering the chip complexity and preparing solutions for advanced CMOS technologies

12. 12 CONFIDENTIAL Workshop on Information Technology March 2005 - Shanghaï Technical challenges FRESH : “Flexible and Reconfigurable Embedded Software and Hardware”  Prototyping Integrated Circuits  Telecom and Multimedia Applications: e.g., MC-CDMA Chip  Reconfigurability in terms of computing, control and communication resources  Network on Chip based architecture  Asynchronous mechanisms for communication purposes  Associated design flow and mapping tools

13. 13 CONFIDENTIAL Workshop on Information Technology March 2005 - Shanghaï FRESH Generic Platform Architecture Interconnexion Network IPs HW ………. SW IPs Reconfigurable Computing Reconfigurable Computing µProc MEM I/O FPGA µProc DSP µProc DSP Interface Other system Other system CO-DESIGN TOOLS & DEVELOPMENT ENVIRONMENT Integrated Circuit Prototyping integrated circuit, e.g. for MC-CDMA Flexible & Reconfigurable ICs Integration of a large number of computing resources Well-defined interfaces between communication and computing resources Communication systems based on a distributed network Network extension outside IC to increase functionalities & performances Associated co-design tools

14. 14 CONFIDENTIAL Workshop on Information Technology March 2005 - Shanghaï Supercomputer architecture Computing (parallelism and reconfigurable computing) Racks Processing boards boards Control (task scheduling, parallelism control and reliability) Host Sparc Sparc ALU Reconf Registers PU Processing Unit UC + Mem PE Processors PE User

15. 15 CONFIDENTIAL Workshop on Information Technology March 2005 - Shanghaï RISC core L1 L2 Scheduling, … RISC core L1 RISC core L1 RISC core L1 RISC core L1 RISC core L1 Switch and interconnection OS RPU fg core L1 RPU cg core L1 Multicore architecture component ם TLP et RPU ם Reconfigurable Interconnections ם Complexity managment ם Embedded reliability ם Energy managment ם Advanced technologies ם Reconfigurable coprocessors Control Computing