3. InputsMetricsCodeResults

4. MAIN MEMORY core Interconnection network Private data (LI) cache Cache controller core Cache controller Private data (LI) cache MULTICORE PROCESSOR CHIP

5. InputsMetricsCodeResults

6. Name#coresC Latency M Latency M Blocks Cache Blocks Input Size Store % Number of invalidate messages in MSI and MESI Number of write-backs in MSI and MOSI L18310010K1K 0 L28310010K1K 40 L38310010K1K 80 M18310010K1K10K0 M28310010K1K10K40 M38310010K1K10K80 H18310010K1K100K0 H28310010K1K100K40 H38310010K1K100K80 InputsMetricsCodeResults

7. Name#coresC Latency M Latency M Blocks Cache Blocks Input Size Store % Sensitivity of write-backs to the cache size MC18310010K1010K50 MC28310010K10010K50 MC28310010K1K10K50 Sensitivity of write-backs to the # of cores MW12310010K10010K50 MW24310010K10010K50 MW38310010K10010K50 InputsMetricsCodeResults  Goals: number of invalidate messages (MESI), number of write backs (MOSI)

8. InputsMetricsCodeResults

9. InputsMetricsCodeResults

10. InputsMetricsCodeResults

11. InputsMetricsCodeResults

12. InputsMetricsCodeResults

13. InputsMetricsCodeResults

14. InputsMetricsCodeResults

16. IntroductionSnoopingDirectoryConclusion

17. Name#coresC Latency M Latency M Blocks Cache Blocks Input Size Store % Number of invalidate messages in MSI and MESI Number of write-backs in MSI and MOSI L18310010K1K 0 L28310010K1K 40 L38310010K1K 80 M18310010K1K10K0 M28310010K1K10K40 M38310010K1K10K80 H18310010K1K100K0 H28310010K1K100K40 H38310010K1K100K80 InputsMetricsCodeResults

18. 9900 3672 2863 7299 5698 35622 27762 71739 55818 357561 277942 713178 554708 96230 00 InputsMetricsCodeResults

19. 00 133 131 445 443 3716 3676 7619 7603 42451 38638 79834 78389 00 00 InputsMetricsCodeResults

20. InputsMetricsCodeResults 111423 102651 100922110634 100904 99612 880901 978997 824215 930590 3622474 7334447 4049448 8026737 1116330 965589 12580649 10157839

21. InputsMetricsCodeResults Name#coresC Latency M Latency M Blocks Cache Blocks Input Size Store % Sensitivity of write-backs to the cache size MC18310010K1010K50 MC28310010K10010K50 MC28310010K1K10K50

22. 4949 9953 49484901 9676 4717 2848 6583 2328 InputsMetricsCodeResults

23. InputsMetricsCodeResults Name#coresC Latency M Latency M Blocks Cache Blocks Input Size Store % Sensitivity of write-backs to the # of cores MW12310010K10010K50 MW24310010K10010K50 MW38310010K10010K50

24. 1 0.73 1 0.63 1 InputsMetricsCodeResults

25. Interconnection network MAIN MEMORY core Private data (LI) cache Cache controller Directory controller Directory MAIN MEMORY core Private data (LI) cache Cache controller Directory controller Directory In this presentation, we present the result of implementing multiprocessor system model with distributed directory

27. … Directory controller Cache Block Cache controller Core Cache controller Core Cache controller Core Cache controller sends request to directory

28. Cache controller Core … Cache controller Directory controller Cache Block Core Cache controller Core bottleneck

29. Cache controller Core … Cache controller Directory controller Cache Block Core Cache controller Core Directory controller Cache controller responses to every request by unicasting message

30. Messages typesStates

34.  MOSI_protocol_cache_request: Executing cache controller request  MOSI_protocol_directory_request: Executing directory controller response  I_state_cache: Performing cache actions when it is in I state  Transition_I_to_SD: Performing cache actions when it is in I state and wants to change to S state with condition D  Directory_I: Performing directory action upon receiving message on cache controller for a block in I state

35.  MOSI protocol:  Number of cores: 8; Number of request/cycle: 4 L1 Block Size (bytes) Write-Back/ Memory References 16 613779 3234277 6417180 1288537 Write backs L1 cash size (KB) Write backs L1 block size (bytes) Block size =16 bytes Cache size = 128 bytes

36. Number of write backs mean(MOSI/MSI) = 0.7816

37. IntroductionDirectorySnoopingConclusion Number of blocks/cache: 1000 Number of cache:100 Number of request/cycle: 4 Number of stalls mean(MOSI/MSI) = 1.1002

38. Number of blocks/cache: 1000 Number of cache:100 Number of request/cycle: 4 Number of cycles mean(MOSI/MSI) = 1.459

39. Number of blocks/cache: 1000 Number of cache:100 Number of request/cycle: 4 mean(MOSI/MSI) = 1.345mean(MOSI/MSI) = 1.273

40.  [1] - Daniel J. S. Mark D. H. David A. W., “A Primer on Memory Consistency and Cache Coherence,” Morgan Claypool Publishers, 2011.  [2] – Suleman, Linda Bigelow Veynu Narasiman Aater. "An Evaluation of Snoop- Based Cache Coherence Protocols."  [3] – Tiwari, Anoop. Performance comparison of cache coherence protocol on multi-core architecture. Diss. 2014.  [4] – Chang, Mu-Tien, Shih-Lien Lu, and Bruce Jacob. "Impact of Cache Coherence Protocols on the Power Consumption of STT-RAM-Based LLC."  [5] – CMU 15-418: Parallel Architecture and Programming. Lecture Series. Spring 2012