1. ECE 353 Introduction to Microprocessor Systems Michael Schulte Week 13

2. Administration Homework #6 due Friday, May 9 th Reading for week 13 (serial I/O) Textbook Chapter 10 ADUC p. 62-71 Supplement #4 (Learn@UW) Final exam on Saturday, May 17 th from 7:45am to 9:45am in 3418 EH Cumulative exam covering Modules 1-6 + Serial I/O (week 13) Review this Friday Quiz #3 returned

3. Quiz #3 Data High: 92%, Low: 66.5% Avg: 79%, Median: 80% Grade Breakdown for Quiz #3 85-100 A 80-84.9AB 75-79.9B 70-74.9BC 65-69.9C

4. Topics Serial I/O Serial data transfer concepts Asynchronous and synchronous transfers UARTs  UART Interrupts Circular buffering RS-232 and flow control ADuC7026 Serial Peripherals UART SPI I 2 C

5. Serial I/O Concepts Serial communication transmits data one bit at a time. Why? Data transfers over long distances Reduced pin and interconnection count Easier to route with switches Eliminates parallel bus skew issues Terminology Communications channel Simplex vs. duplex vs. half-duplex Transmission rates (baud rate vs. bit rate) Information codes Data Frames

6. Serial Communications Concepts - Morse Code A.- N -. 1.----..-.-.- B -... O --- 2..---, --..-- C -.-. P.--. 3...-- ?..--.. D -.. Q --.- 4....- ( -.--. E. R.-. 5..... ) -.--.- F..-. S... 6 -.... - -....- G --. T - 7 --... ".-..-. H.... U..- 8 ---.. _..--.- I.. V...- 9 ----. '.----. J.--- W.-- 0 ----- : ---... K -.- X -..- / -..-. ; -.-.-. L.-.. Y -.-- +.-.-. $...-..- M -- Z --.. = -...-

7. Asynchronous vs. Synchronous Asynchronous Communication No common clock signal between transmitter and receiver Synchronization must be established on a per frame basis Example – RS232 Synchronous Communication Clock is transmitted in addition to data, or is recovered from data signalrecovered from data signal Often includes a framing signal as well Example – I 2 S Example – I 2 S

8. Asynchronous Data Transfer RS-232 signal phases Idle Start bit Data Parity Stop bit Idle or Start next frame

9. UARTs Universal Asynchronous Receiver- Transmitter Basic UART construction Practical UARTs  Complex I/O device functionality encapsulated behind a register interface Control Status Data  FIFOs  MODEM control signals

10. UART Interrupts UARTs often can generate interrupts for a number of conditions Receive data ready Receive data error  Framing, parity, overrun Modem signal status changes Transmitter buffer empty  If data available, just sent it  If no data available and level sensitive interrupts, ISR should mask the transmit interrupt and the program putting data in the queue should unmask it

11. Circular Buffering Implement simple FIFO queueing in software to minimize data movement. Some CPUs (especially DSPs) implement circular addressing modes in hardware for speed.

12. RS-232 RS-232 is one of many physical-level standards for serial communications. Selected serial communications standards RS-232 defines many aspects of the serial data channel Equipment definitions Connector construction and pin-outspin-outs Modem control signals Signal levels RS-232 line drivers and receiversline drivers and receivers

13. Flow Control A serial channel may deliver data faster than the receiving device can process. Flow control gives the receiver a way to signal the transmitter to stop transmission. Flow control can be implemented as Software  XON/XOFF flow control protocol Hardware  RTS/CTS

14. ADuC7026 Serial Peripherals There are 4 serial peripherals on the ADuC7026; a UART and 3 synchronous ports (SPI and I 2 C) There are ten pins that are used by the serial peripherals in two modes

15. ADuC7026 UART COMCON0 Basic frame configuration Baud rate Basic baud rate divider Fractional baud rate divider

16. ADuC7026 SPI Port The Serial Peripheral Interface (SPI) port can be configured as a master or slave (shown below) SPI consists of 2 unidirectional data lines, a clock line, and a chip select line

17. ADuC7026 I 2 C Ports The Inter-Integrated Circuit (I 2 C) ports can operate as master or slave I 2 C supports multi-master buses using just 2 bidirectional lines (clock and data)  Both use open-drain drivers and pull-up resistors  Collisions can occur without damage – recognized when a line will not return high after it is released

18. Asynchronous Communications - RS232 Framing Back What do you need to know in order to figure out what the data is? When should the data be sampled?

19. Synchronous Communications Back frame

20. Clock Recovery Back

21. Serial Communications Standards Back

22. RS-232 Connectors Back

23. RS-232 Signal Levels Back Data signals are shown. Control signals have opposite polarity.

24. MAX221 Back

25. Basic UART Construction Back