1. The GNU in RADIO Shravan Rayanchu

2. SDR Getting the code close to the antenna –Software defines the waveform –Replace analog signal processing with Digital signal processing Why? –Flexibility, time to market, reliable –Its all about the stack : GPRS/ WiFi / WiMax

3. SDR Possibilities …? –TX/RX on multiple channels simultaneously –Better spectrum usage –“Cognitive radios” Disadvantages –Higher power consumption (GPU vs ASIC) –More MIPS! –Higher cost (as of today)

4. GNU RADIO Platform for –Experimenting with digital communications –Signal processing using commodity hardware Free software! http://www.gnu.org/software/gnuradio/

5. A TYPICAL SDR

6. ADC Sampling Rate –Rate at which you sample the analog signal –Determines what frequency can be handled Dynamic range –Number of signal levels –Quantization error SNR = 6.02N + 1.76dB

7. Sum of sinusoids: Sigma a i Sin (2 pi f i t) Sampling

8. Sin (2 pi f c nt s )= Sin (2 pi f c nt s + 2 pi m)= Sin (2 pi nt s (f c + m/n f s )) f c + k f s Sampling We need a LOW PASS FILTER !

9. Sampling

10. Nyquist Criteria Sampling freq > Twice the max. frequency component in the signal of interest

11. ALIASING ADCs in USRP: 64 Msps  32 Mhz How to receive 2.4 Ghz ? RF Front end

12. RF Front End: Down conversion LPF VCO LPFADC Mixer: sinusoid of (RF-IF) Intermediate Frequency (IF)

13. RF Front Ends 50 - 860 Mhz RX 400 – 500 Mhz Transceiver 2300 – 2900 Mhz Transceiver –Bandpass filter (2.4 to 2.483 Ghz)

14. USRP

15. Universal Software Radio Peripheral –To rapidly design powerful, flexible software radio platforms What does it have? –FPGA (ALTERA Cyclone) –Mixed signal processor (AD 9862) –Slots for 4 daughter boards (2 TX, 2 RX)

16. Boot sequence: two programmable components USB Controller (Cypress FX2): 8051 code FPGA (ALTERA Cyclone): Verilog

17. USRP Four 12-bit ADC, 64 Msps –Sub-multiples are also possible: 42.66 Msps, 32 Msps, 25.6 Msps and 21.33 Msps –Decimation helps –IF has to be < 32 MHz Four 14-bit DAC 128 Msps –Max. output 50 Mhz Four I/Os simultaneously if we use real sampling, Two I/Os for complex sampling; synchronized clocks Each daughter board has access to 2 DACs and 2 ADCs Why Different boards ? –different RFs  same IF

18. Mux usage: http://webpages.charter.net/cswiger/usrp_diagra ms/

19. USRP Four Digital Downconverters (DDCs) –FPGA with CIC Filters –Programmable decimation rate –Low pass filter Two Digital Upconverters (DUCs) –AD 9862 –Programmable interpolation rate USB 2.0 (480 Mbps, peak)

21. RX PATH

22. DDC : IF  Complex Baseband

23. AD 9862 Block D: The "Fine Modulator" -- this is a digital up-converter Block C: Interpolation filter (we interpolate by 4 in the AD9862) Block B: The "Coarse Modulator" Block A: The actual DACs. TX PATH

24. GNU Radio Software Architecture Library of signal processing blocks (C++) –Ex: sources, sinks, others Input, output ports, types, ‘work function’ Create a ‘flow graph’ : vertices are blocks and edges represent the data flow (Python) SWIG, FFTW, Boost …

25. Lets look into some code!

26. GENERATE DIAL TONE

32. Frequency Modulation

39. Spectrum Sensing

45. 6 Mhz Limit  USB 2.0 limit  32 MBytes/sec ADC 64 Msps  32 Mhz chunk 8 Msps w/ 16 bit I/Q samples – 8 * 2 * 2 = 32 Mbytes/sec – 4 Mhz * 2 = 8 Mhz (Quadrature sampling) –Discard 1/4 of bins ~ 6 Mhz Decimation (8, 256) Interpolation (16,256)

46. Spectrum Mask

47. Spectrum Sensing Tune : 0.001 sec, Dwell : 0.1 sec, Step: 0.5 Mhz, FFT : 1 Mhz wide

48. Spectrum Sensing Tune : 0.001 sec, Dwell : 0.1 sec, Step: 1 Mhz, FFT : 1 Mhz wide

49. Spectrum Sensing

50. Tune : 0.001 sec, Dwell : 0.01 sec, Step: 1 Mhz, FFT : 1 Mhz wide

51. Spectrum Sensing Tune : 0.001 sec, Dwell : 0.01 sec, Step: 1 Mhz, FFT : 1 Mhz wide

52. CSMA

57. Complex samples from USRP

58. CSMA Complex samples from USRP

59. Spectrum

60. CSMA Complex samples from USRP

61. CSMA Complex samples from USRP Filter to get the actual channel we want

62. CSMA Complex samples from USRP Filter to get the actual channel we want

63. CSMA Complex samples from USRP Filter to get the actual channel we want

64. CSMA Complex samples from USRP Filter to get the actual channel we want Demodulate to get ones and zeroes

65. CSMA Complex samples from USRP Filter to get the actual channel we want Demodulate to get ones and zeroes

66. CSMA Complex samples from USRP Filter to get the actual channel we want Demodulate to get Get the SYNC Vector ones and zeroes

67. CSMA Complex samples from USRP Filter to get the actual channel we want Demodulate to get Get the SYNC Vector ones and zeroes

68. CSMA Complex samples from USRP Filter to get the actual channel we want Demodulate to get Get the SYNC Vector ones and zeroes We have the pkt now

69. CSMA Complex samples from USRP Filter to get the actual channel we want Demodulate to get Get the SYNC Vector ones and zeroes We have the pkt now Carrier Sense RX CALLBACK

70. Some numbers.. Time to switch freq ~ 0.001 sec (Have to verify) Modulation: –GMSK, [ DBPSK, DQPSK didn’t work  ] –Bit rate = 500k [ CPU Maxed out  ] Throughputs: –UDP: 520 kbps ! (PHY: 500 kbps) : Error in Netperf ? –TCP: 20 ~ 80 Kbps

71. Channel 1, less tries 2.412 (Channel 1), 3.8% pkts in error

72. Channel 1, Ping flood, More tries

73. Channel 1, Ping source, More tries 4% error (throughput very less)

74. Channel 6 2.3% pkts in error

75. 2.423 Ghz ~ 1.6% pkts in error

76. 2.562 Ghz 0% pkts in error

77. Channel 1, Ping source CS_Thresh = 70, 50 Error was ~ 4 % !!

79. What do we have? Multiple modulations: –BPSK, QPSK, GMSK, QAM (soon) Symbol rates / bandwidth Pulse shape filtering (?) Carrier Frequency Power Payload size CRC..