1. IHP Im Technologiepark 25 15236 Frankfurt (Oder) Germany IHP Im Technologiepark 25 15236 Frankfurt (Oder) Germany www.ihp-microelectronics.com © 2010 - All rights reserved Low Power Sensor Node Processor Architecture G. Panić, T. Basmer. K. Tittelbach-Helmrich, L. Lopacinski

2. IHP Im Technologiepark 25 15236 Frankfurt (Oder) Germany www.ihp-microelectronics.com © 2010 - All rights reserved 2 Outline Introduction Motivation Processor System Architecture Implementation Conclusion

3. IHP Im Technologiepark 25 15236 Frankfurt (Oder) Germany www.ihp-microelectronics.com © 2010 - All rights reserved 3 Introduction – Wireless Sensor Networks Sensor Networks A [wireless] network of low cost, densely deployed, untethered sensor nodes Applications Industrial, Homeland Security, Telemedicine, Context Sensitive Systems

4. IHP Im Technologiepark 25 15236 Frankfurt (Oder) Germany www.ihp-microelectronics.com © 2010 - All rights reserved 4 WSN – Sensor Node Modern Sensor Nodes UC Berkeley: COTS Dust UC Berkeley: Smart Dust UCLA: WINS Rockwell: WINS JPL: Sensor Webs IHP Tandem Stack IHP Feuerwhere

5. IHP Im Technologiepark 25 15236 Frankfurt (Oder) Germany www.ihp-microelectronics.com © 2010 - All rights reserved 5 Motivation General Goals: Design a sensor node platform for future WSN applications Low power processing Reuse flexibility SensoricProcessingRadio Sensor Node: Three basic op. units: Sensoric, Processing, Radio Memory for software Battery powered Memory

6. IHP Im Technologiepark 25 15236 Frankfurt (Oder) Germany www.ihp-microelectronics.com © 2010 - All rights reserved 6 Power Issues The most important limitation factor is POWER! [ITRS 2002]

7. IHP Im Technologiepark 25 15236 Frankfurt (Oder) Germany www.ihp-microelectronics.com © 2010 - All rights reserved 7 Sensor Node – Power Optimization High Level Of Integration single chip solution, MTCMOS Optimized Node Architecture reduced on-chip communication, DMA, hardware accelerators Advanced Power Saving Methodologies power gating, DFVS, multi-voltage design Low Power Radio picoRadio, wake-up concept Non-Standard Approach asynchronous logic, latch-based design, etc.

8. IHP Im Technologiepark 25 15236 Frankfurt (Oder) Germany www.ihp-microelectronics.com © 2010 - All rights reserved 8 IHP Sensor Node Platform Retention Wake-up Data Storage RAM Sensors Preprocessor CPU Baseband MAC Hw Accelerator AFE A/D I/O Ports Power Gating Controller System Timer Debug I/F ROM Power-gating partitions SPI Objectives: low power processing -> async CPU wireless connectivity -> BB, SPI sensor connectivity -> Digital I/O, SPI Challenges: peripheral interface to async CPU peripheral register access glitch free control logic

9. IHP Im Technologiepark 25 15236 Frankfurt (Oder) Germany www.ihp-microelectronics.com © 2010 - All rights reserved 9 Sensor Node – Processor Architecture IPMS430x – low power asynchronous TI MSP430x clone, I2C debug port Timer – 3 CAP/CMP regs, PWM, clock divider Digital I/O – 2 simple I/Os and 2 with interrupt capability SPI master – edge selection, burst mode Baseband - DIN EN 13757-4, DSSS extended IPMS 430x MUXMUX Timer BB P1 SPI P2P3P4 RAM ROM Debug (I2C)

10. IHP Im Technologiepark 25 15236 Frankfurt (Oder) Germany www.ihp-microelectronics.com © 2010 - All rights reserved 10 Implementation - RTL Peripheral Interface (Clock Generation) Addr Latch Addr Demux address csl_n csh_n p1_sel p1_clk pn_sel pn_clk delay mclk addr csl_n csh_n px_sel px_clk outputs

11. IHP Im Technologiepark 25 15236 Frankfurt (Oder) Germany www.ihp-microelectronics.com © 2010 - All rights reserved 11 Implementation - RTL Glitch Filtering Reg File Ctrl Logic S R glitch filter delay input delayed_input output set <= '1' when reg(1 downto 0) = "01" else '0'; reg[1:0] changes from "00" to "11" -> potential glitch reg[0] reg[1]

12. IHP Im Technologiepark 25 15236 Frankfurt (Oder) Germany www.ihp-microelectronics.com © 2010 - All rights reserved 12 Implementation - RTL Peripheral Register Access cpu_clk periph_clk p_sel cpu_data periph_data0 0 1 1 D - cpu access has priority! - peripheral clock can be gated by software to avoid conflicts

13. IHP Im Technologiepark 25 15236 Frankfurt (Oder) Germany www.ihp-microelectronics.com © 2010 - All rights reserved 13 Implementation - Synthesis Total Dynamic Power (uW) Cell Leakage Power (uW) Total Cell Area (mm 2 ) IPMS430x4104.40.292 P1-P2 (ir)1540.10.018 P3-P4870.080.011 Timer3440.80.062 Baseband5395.30.507 SPI1820.20.023 Mux1030.080.013 Core + Mem69311.84.675 System + IO124412.16.567 target frequency 20 MHz, worst case conditions post-synthesis results

14. IHP Im Technologiepark 25 15236 Frankfurt (Oder) Germany www.ihp-microelectronics.com © 2010 - All rights reserved 14 Implementation - Layout Size: 12,6 mm 2 Nr. of Pads: 115 (91 sig, 24 p/g) Max Freq: 20 MHz Power (Core): 4-5 mW@20MHz The chip has been produced and successfully tested!

15. IHP Im Technologiepark 25 15236 Frankfurt (Oder) Germany www.ihp-microelectronics.com © 2010 - All rights reserved 15 Results Comparison IHP IPMS430x Tmote Sky MSP430F1611 PeripheralsSPI, BB, I/O, Timer ATimer A, UART, DMA, ADC, DAC, I/O Memory4kB RAM + 1kB ROM (1 MB max) 10kB RAM, 48kB Flash, 128B storage (64kB max) Package128 pin64 pin Power0.25mW/MHz @ 2.5 V1mW/MHz @ 3V Max Frequency20 MHz8 MHz IHP IPMS430x vs Tmote Sky MSP430F1611

16. IHP Im Technologiepark 25 15236 Frankfurt (Oder) Germany www.ihp-microelectronics.com © 2010 - All rights reserved 16 Conclusion IPMS430x based system designed low power, low CPU core area, large address space (1MB) additional baseband functionality external Flash interface (disadvantage) Design challenges resolved peripheral interface, glitch filtering, register access Trade-Off implementation effort testability of asynchronous logic undiscovered errors on asynchronous paths Future Work integration of additional components: Flash, DMA, AFE, etc. power gating implementation reduction of pads number

17. IHP Im Technologiepark 25 15236 Frankfurt (Oder) Germany www.ihp-microelectronics.com © 2010 - All rights reserved 17 The End Thanx Thanx Any Questions Any Questions ???