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Published byBaldwin Lloyd Modified over 9 years ago
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Metallization: Contact to devices, interconnections between devices and to external Signal (V or I) intensity and speed (frequency response, delay)
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Issues in VLSI Metallization Speed: switching speed, RC delay Intensity: electromigration ( I ), electric breakdown ( V ) Stability: contact interface, stable I-V characteristics Voltage drop: IR drop reduces voltage on transistor Area: connection wires have to be narrow as device density increases
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Multi-level Metallization Lower levels: fine connections to individual devices Upper levels: thicker/wider common connections
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Multi-level metal connections
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Pit Formation of Al Contact with Si High solubility of Si in Al (~1%) Al spikes
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Silicide Contacts
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Phase Diagram and Formation Sequence of Silicide
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Salicide (Self-aligned silicide layer) N-channel MOS with poly Si gate Ti deposition and annealing, TiSi 2 formation at source, drain and gate Etch away unreacted Ti Apply dielectrics and final metallization with Al
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Multi-level Metallization
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Plug Filling
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Chemical Mechanical Polishing (CMP)
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Damascene processes Dual damascene Metal plugs in planar SiO 2 Interlayer dielectric deposit Trench patterning & RIE for metal lines Metal deposition CMP Single barrier layer and metal deposition steps, same metal for plugs and lines
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Electromigration Effects Void Pile-up Electron wind and field-driven atomic migration Bamboo-structured wire Electromigration-resistant
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Triple diffusion 2-sided diffusion Double-diffused epitaxial p-well (tub) n-well Epitaxy double-well Device Isolation
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CMOS Technology CMOS inverter Simple CMOS layout
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Twin-well CMOS process
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Lateral Isolation Localized oxidation isolation (LOCOS) Trench isolation Oxidation isolation
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Simple MOS process (a) Source & drain p + diffusion (b) Wet oxidation for field oxide (c) Dry oxidation for gate oxide (d) Al metallization for gate and contacts to S & D
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Poly-Si gate NMOS process Field oxide growth and opening etching Gate oxide growth and poly-Si deposit Gate, source & drain n + diffusion PSG CVD, lithography and metallization
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General Process Integration Considerations for ULSI In mask and process designs, tolerances for variations in line width, junction depth and width, depletion zone width, film thickness, mask-making and alignment Use self-aligned process if possible: e.g. source & drain implantation, salicide process Step heights (vertical profile variation) must ensure a positive focus margin (FM) Large process window and small sensitivity: tolerate variation in equipment performance On-line monitoring of control parameters
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Wafer with IC Chips Thin film pads for wire bonding Bonding & Packaging
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Plastic-encapsulated package Back side of IC chip bond to a metallized ceramic substrate Au wires connecting the IC and pins
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Wire bonding process
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Flip-chip bonding with Pb-Sn solder ball in contact with a ceramic substrate More interconnect pad (>100) allowed Shorter connection length, less coupling
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