1. Modern VLSI Design 4e: Chapter 4 Copyright  2008 Wayne Wolf Topics n Switch networks. n Combinational testing.

2. Modern VLSI Design 4e: Chapter 4 Copyright  2008 Wayne Wolf Boolean functions and switches pseudo-AND pseudo-OR

3. Modern VLSI Design 4e: Chapter 4 Copyright  2008 Wayne Wolf Driving switch outputs n If switch network output is not connected to power supply through switch path, output will float. n Switch network inputs may be connected to power supply or logic signals.

4. Modern VLSI Design 4e: Chapter 4 Copyright  2008 Wayne Wolf Switching logic signals b’ a b a’ ab’ + a’b

5. Modern VLSI Design 4e: Chapter 4 Copyright  2008 Wayne Wolf Switch multiplexer

6. Modern VLSI Design 4e: Chapter 4 Copyright  2008 Wayne Wolf Charge sharing n Interior nodes in a switch network may not be driven. n Charge can accumulate on small parasitic capacitances. n Shared charge can produce erroneous output values.

7. Modern VLSI Design 4e: Chapter 4 Copyright  2008 Wayne Wolf Charge division n At undriven nodes, charge is divided according to capacitance ratio.

8. Modern VLSI Design 4e: Chapter 4 Copyright  2008 Wayne Wolf Charge sharing example n Long chains of switches have intermediate nodes which may be disconnected from power supplies. C ab C ia C bc

9. Modern VLSI Design 4e: Chapter 4 Copyright  2008 Wayne Wolf Charge over time timeiC ia aC ib bC bc cC 011111111 100100101 2 0001/211/201 3 0 001/203/413/4 4 0 00003/403/4 5 0 003/813/803/4

10. Modern VLSI Design 4e: Chapter 4 Copyright  2008 Wayne Wolf Avoiding charge sharing n Make sure that for every input combination there is a path from the power supply to the output.

11. Modern VLSI Design 4e: Chapter 4 Copyright  2008 Wayne Wolf Manufacturing testing n Errors are introduced during manufacturing. n Testing verifies that chip corresponds to design. n Varieties of testing: –functional testing; –performance testing (binning chips by speed). n Testing also weeds out infant mortality.

12. Modern VLSI Design 4e: Chapter 4 Copyright  2008 Wayne Wolf Testing and faults n Fault model: –possible locations of faults; –I/O behavior produced by the fault. n Good news: if we have a fault model, we can test the network for every possible instantiation of that type of fault. n Bad news: it is difficult to enumerate all types of manufacturing faults.

13. Modern VLSI Design 4e: Chapter 4 Copyright  2008 Wayne Wolf Stuck-at-0/1 faults n Stuck-at-0/1: logic gate output is always stuck at 0 or 1, independent of input values. n Correspondence to manufacturing defects depends on logic family. n Experiments show that 100% stuck-at-0/1 fault coverage corresponds to high overall fault coverage.

14. Modern VLSI Design 4e: Chapter 4 Copyright  2008 Wayne Wolf Testing procedure n Testing procedure: –set gate inputs; –observe gate output; –compare fault-free and observed gate output. n Test vector: set of gate inputs applied to a system.

15. Modern VLSI Design 4e: Chapter 4 Copyright  2008 Wayne Wolf Stuck-at faults in gates abOKSA0SA1 00101 01101 10101 11001 abOKSA0SA1 00101 01001 10001 11001 NAND NOR

16. Modern VLSI Design 4e: Chapter 4 Copyright  2008 Wayne Wolf Testing single gates n Three ways to test NAND for stuck-at-0, only one way to test it for stuck-at-1. n Three ways to test NOR for stuck-at-1, only one way to test it for stuck-at-0.

17. Modern VLSI Design 4e: Chapter 4 Copyright  2008 Wayne Wolf Testing combinational networks n 100% coverage: test every gate for –stuck-at-0; –stuck-at-1. n Assume that there is only one faulty gate per network. n Most networks require more than one test vector to test all gates.

18. Modern VLSI Design 4e: Chapter 4 Copyright  2008 Wayne Wolf Multiple test example

19. Modern VLSI Design 4e: Chapter 4 Copyright  2008 Wayne Wolf Example n Can test both NANDs for stuck-at-0 simultaneously (abc = 000). n Cannot test both NANDs for stuck-at-1 simultaneously due to inverter. Must use two vectors. n Must also test inverter.

20. Modern VLSI Design 4e: Chapter 4 Copyright  2008 Wayne Wolf Stuck-at-open/closed model n Models transistors always on/off.

21. Modern VLSI Design 4e: Chapter 4 Copyright  2008 Wayne Wolf Stuck-open behavior n If t 1 is stuck open (switch cannot be closed), there can be no path from V DD to output capacitance. n Testing requires two cycles: –must discharge capacitor; –try to operate t 1 to see if capacitor can be charged.

22. Modern VLSI Design 4e: Chapter 4 Copyright  2008 Wayne Wolf Delay fault n Delay falls outside acceptable limits: –gate delay fault assumes that all delays are lumped into one gate; –path delay fault models delay problems along path through network. n Delay problems reduce yield: –performance problems; – functional problems in some types of circuits.

23. Modern VLSI Design 4e: Chapter 4 Copyright  2008 Wayne Wolf Combinational network testing Two parts to testing: –controlling the inputs of (possibly interior) gates; –observing the outputs of (possibly interior) gates.

24. Modern VLSI Design 4e: Chapter 4 Copyright  2008 Wayne Wolf Combinational testing example

25. Modern VLSI Design 4e: Chapter 4 Copyright  2008 Wayne Wolf Testing procedure n Goal: test gate D for stuck-at-0 fault. n First step: justify 0 values on gate inputs. n Work backward from gate to primary inputs: –w1 = 0 (A output = 0); –i1 = i2 = 1.

26. Modern VLSI Design 4e: Chapter 4 Copyright  2008 Wayne Wolf Testing procedure, cont’d n Observe the fault at a primary output: –o1 gives different values if D is true/faulty. n Work forward and backward: –F’s other input must be 0 to detect true/fault. –Justify 0 at E’s output. n In general, may have to propagate fault through multiple levels of logic to primary outputs.

27. Modern VLSI Design 4e: Chapter 4 Copyright  2008 Wayne Wolf Fault masking Redundant logic can mask faults:

28. Modern VLSI Design 4e: Chapter 4 Copyright  2008 Wayne Wolf Redundancy example n Testing NOR for SA0 requires setting both inputs to 0. n Network topology ensures that one NOR input will always be 1. n Function reduces to 0: –f = (ab)’ + b’ = a’ + b’ + b = 0.

29. Modern VLSI Design 4e: Chapter 4 Copyright  2008 Wayne Wolf Redundancies and testing n Redundant logic cannot be controlled. n Observations requiring control of redundant logic may not be possible. n Redundant logic should be minimized to eliminate redundancy. Redundancies can introduce delay faults and other problems.