1. 3rd Annual Review Meeting Sinaia, Romania, February 21-22, 2005 REASON (IST-2000-30193) Third Annual Report Workpackage 3 Raimund Ubar Tallinn Technical University raiub@pld.ttu.ee

2. 3rd Annual Review Meeting, Sinaia, Romania, February 21-22, 2005 Tasks and Goals WP3 is devoted to –training in design for testability of SoC, and –developing research skills and creativity by –development of courses (Task 3.1), tools (Task 3,2), research scenarios (Task 3.3), and –dissemination of new methods and tools in tutorials, seminars and workshops (Task 3.4)

3. 3rd Annual Review Meeting, Sinaia, Romania, February 21-22, 2005 WP3 Timeline The development activities in T3.1, T3.2, and T3.3 were mainly related to new initiatives and AGBOT Environment AGBOT

4. 3rd Annual Review Meeting, Sinaia, Romania, February 21-22, 2005 New Activities in T3.2 & T3.3 Task 3.2. Teaching, training and research environment Task 3.3. Research scenarios Internet based “living pictures” for training (WP8) –development of research scenarios Tool development for SW based lab research (WP3) –interfaces for joint use of tools Educhip for HW based lab research (WP9) –software development for EduChip –Research scenarios for EduChip

5. 3rd Annual Review Meeting, Sinaia, Romania, February 21-22, 2005 Contribution to WP3 in 2004 Teaching Materials T3.1 Tools T3.2 Training Actions T3.4 Research Scenarios T3.3 TULC, TTU, WUT TTU, IISAS, TULC, FEISTU TULC, VSTU, IISAS, FEISTU BSU,TTU,WUT TTU,TUI,TULC IISAS, FEISTU, VSTU, LPU, WUT,BSU,TUS

6. 3rd Annual Review Meeting, Sinaia, Romania, February 21-22, 2005 Cooperation in 2004 IISAS FEISTU TUS PUB WUT TTU TULC TUI Tools & Research Scenarios AGBOT Training Actions VSTU BSU TUL KTU

7. 3rd Annual Review Meeting, Sinaia, Romania, February 21-22, 2005 Cooperation between other WPs Task 3.2 Tools SW/HW Environment WP8 Applets WP9 Educhip Task 3.3. Research training scenarios Development of the research environment in cooperation with WP8 and WP9

8. 3rd Annual Review Meeting, Sinaia, Romania, February 21-22, 2005 Cooperation between other WPs WP10 Conferences MIXDES DDECS EWDTW BEC WP2 Smolenice WP7 Sinaia WP3 Task 3.1. Course development Joint tutorials:

9. 3rd Annual Review Meeting, Sinaia, Romania, February 21-22, 2005 Task 3.2. Tool integration VHDL/Verilog/ System C Logic synthesis Synopsys/Cadence Gate-Level EDIF EDIF-SSBDD EDIF-ISCAS ISCAS Netlist ISCAS Benchmarks University Software SSBDD VHDL-DD DD Hierarchical ATPG DefGen/Delay IISAS Defect Library Defect/Fault Analysis WUT Turbo-Tester TTU High-Level ATPG KTU Cooperation: IISAS, KTU, TTU, WUT, TULC Optimization of Scan-Based DfT TULC Test Set

10. 3rd Annual Review Meeting, Sinaia, Romania, February 21-22, 2005 Tools for test generation and fault simulation Lab Research Env. - 1 Task 3.2 Design Error Diagnosis Test Generation BIST Emulation Design Test Set Levels: Gate Macro RTL Fault Table Test Set Optimization Methods: BILBO CSTP Hybrid Fault Simulation Faulty Area Circuits: Combinational Sequential Logic Simulation Formats: EDIF AGM Defect Library Hazard Analysis Data Specifi- cation Algorithms: Deterministic Random Genetic Multivalued Simulation Fault models: Stuck-at faults Physical defects

11. 3rd Annual Review Meeting, Sinaia, Romania, February 21-22, 2005 Lab Research Env. - 2 DefSim Chip Task 3.2 Educhip based Manual patterns Random patterns Deterministic SAF patterns Deterministic defect-patterns DefSim software (firmware, drivers) DefGen, Turbo Tester, etc. DefSim User Interface Cooperation: IISAS, TTU, WUT

12. 3rd Annual Review Meeting, Sinaia, Romania, February 21-22, 2005. ROM... SoC Core Controller Combining –on-line generated pseudo- random patterns –with pre-generated and stored test patterns Problems : –To find the best characteristics for test generator (PRPG) –To find the best level of mixing pseudo-random test and stored test as the tradeoff between memory cost and testing time Hybrid BIST: CORE UNDER TEST Response Analyzer Test Generator Task 3.3. Scenario: Hybrid BIST

13. 3rd Annual Review Meeting, Sinaia, Romania, February 21-22, 2005 Optimization of Hybrid BIST Cost curves for BIST: Total Cost C TOTAL C Cost of pseudorandom test patterns C GEN Number of remaining faults after applying k pseudorandom test patterns r NOT (k) Cost of stored test C MEM L L OPT k r DET (k)r NOT (k) FC(k)t(k) 115583915.6% 104 27676323.2% 104 36569829.8% 100 49060838.8% 101 54456443.3% 99 1010442157.6% 95 204431168.7% 87 505121878.1% 74 1001614585.4% 52 2001811488.5%41 411317093.0%26 954182897.2%12 156081698.4%7 215311599.5%3 34492399.7%2 45192199.9%1 452010100.0%0

14. 3rd Annual Review Meeting, Sinaia, Romania, February 21-22, 2005 T 3.3. Sc: Hybrid Functional BIST Register block ALU Signatureanalyser Data K M Automatic Test Pattern Generator MUX Register block ALU Signatureanalyser Deterministic test set K M Automatic Test Pattern Generator MUX Functional test Deterministic test Random resistant faults Test patterns are stored in the memory Publications: MIXDES’2004, ETS’2005

15. 3rd Annual Review Meeting, Sinaia, Romania, February 21-22, 2005 To be compared: genetically optimized vs. manually obtained LFSRgenetically optimized vs. manually obtained LFSR original vs. “BISTed” device complexityoriginal vs. “BISTed” device complexity LFSR Config. BIST Emulator Circuit Model (VHDL) Fault Table Circuit Model Test Set Genetic Optimizer WP8: BIST Applet DfT Structure (VHDL) Synthesis Tools Estimated Growth of Complexity Task 3.3. Scenario: BIST design TTU IISAS Other Polynomial, Initial state Cooperation: IISAS, TTU

16. 3rd Annual Review Meeting, Sinaia, Romania, February 21-22, 2005 Events in 2004

17. 3rd Annual Review Meeting, Sinaia, Romania, February 21-22, 2005

21. Events in 2004

22. 3rd Annual Review Meeting, Sinaia, Romania, February 21-22, 2005

26. Events in 2004

27. 3rd Annual Review Meeting, Sinaia, Romania, February 21-22, 2005

29. Events in 2004

30. 3rd Annual Review Meeting, Sinaia, Romania, February 21-22, 2005 Events in 2004 In total: 18 international events out of 21 11 different countries 15 joint events

31. 3rd Annual Review Meeting, Sinaia, Romania, February 21-22, 2005 Geography of Events 4 2 1 2 3 1 1 1 4 1 1

32. 3rd Annual Review Meeting, Sinaia, Romania, February 21-22, 2005 Geography of Lecturers

33. 3rd Annual Review Meeting, Sinaia, Romania, February 21-22, 2005 Participants

34. 3rd Annual Review Meeting, Sinaia, Romania, February 21-22, 2005 Evaluation results

35. 3rd Annual Review Meeting, Sinaia, Romania, February 21-22, 2005 Other activities in 2004 AGBOT – Handbook of Testing (397 pages) 1. Introduction 2. Defects, faults and fault models 3. Test generation techniques and algorithms 4. Design for testability 5. Built-in self-test 6. On-line testing 7. IDDQ testing. 8. Analog test and diagnostics 9. Appendix 1: Tools, that can be used for practical exercises 10.Appendix 2: Philosophy of Mentor test tools The reviewing process is running and simultaneously the reviewed chapters are being formatted for printing.

36. 3rd Annual Review Meeting Sinaia, Romania, February 21-22, 2005

37. 3rd Annual Review Meeting, Sinaia, Romania, February 21-22, 2005

38. Other activities in 2004 IEEE EWDTW - joint East-West event in D&T –Bringing expert skills from West to East Y. Zorian (USA) Virage Logic and TTTC - Embedded Test for SoC Ch. Landrault (France) LIRMM - Memory testing B. Magnhagen (Sweden) DixiCAD - Optical testing –Knowledge transfer from East to West Many experts from leading scientific centers of Russia, Ukraine, Byelorussia shared their knowledge with conference participants Russian Test Tour REASON: 7 lecturers from FEISTU, TTU, TUI, VSTU, WUT RUSSIA: Vladimir, Tomsk, Irkutsk, Vladivostok (134 participants) Meetings - Lviv, Liberec, Lodz, Prague, Bratislava, Sofia

39. 3rd Annual Review Meeting, Sinaia, Romania, February 21-22, 2005 Main achievements: Cooperation To increase the synergy of the project, tight links created to WP8 (distance learning) and WP9 (hardware based experimental research teaching) WP10 (linking tutorials to conferences: MIXDES, BEC, DDECS, EWDTW New links (in 2004): WP2, WP7 (joint tutorials) Continuous extension of the Task 3.2 2003: from tool development to creation of research training environment 2004: web based access to the environment AGBOT – a great book on testing partners: FEISTU, IISAS, TTU, TULC, VSTU (14 authors) a special AGBOT server set up by TULC in order to simplify collaboration New: broader scope, compared to existing books tools for laboratory research theoretical support for Educhips, new lab conception a book for teachers 2-3 times cheaper than IEEE/Kluwer books Intensive joint research - 12 joint publications (8 – 2002, 5 - 2003)

40. 3rd Annual Review Meeting, Sinaia, Romania, February 21-22, 2005 Main achievements: Training 21 tutorials and training actions on Digital and Analog SoC Testing were organized in 11 countries 15 joint tutorials, given by the partners from FEISTU, IISAS, TTU, TULC, VSTU, and WUT 2 WP3 tutorials included into the TTTC TTEP database Expert skills from IEEE and western industry were drawn (in 3 events): –the world leaders in test Y.Zorian (USA), Ch. Landrault (France) were invited to support REASON events at EWDTW in Ukraine –many other western VIPs outside REASON (A.Jerraya, W.Hartenstein, T.Vierhaus, M.Renovell, B.Magnhagen, M.Glesner, H.Tenhunen, S.Kumar) consortium were invited to tutorials in Slovakia and Estonia –a Teaching Tour to Russia was organized in Sept with more than 15 lectures in 4 events all over Russia from Vladimir to Vladivostok Knowledge transfer from East to West –Parts of the REASON WP3 tutorials were invited to be presented in Sweden and Germany (summer school) –MSc and PhD students from West to East

41. 3rd Annual Review Meeting, Sinaia, Romania, February 21-22, 2005 Responses to the 2nd review While the development of 14 tools has been useful to the project, the long terms use will require long-term support. The developments w.r.t. intellectual property should be safeguarded. Commercial alternatives are more suitable for long-term use –The “home made” tools are the results of research which is ongoing, in this way the tool environment is kept alive and continuously updated –good possibility to involve students in research and in updating and improving the tools –because of the web based user access to tools, the support is easier –switching from “home made” to commercial can always be made if possible

42. 3rd Annual Review Meeting, Sinaia, Romania, February 21-22, 2005 Responses to the 2nd review Links and interfaces between the 14 software tools to be improved and clearly documented. Users must have a clear view of the global testing path –The interfaces between partner tools have now been created –also the interfaces and converters to commercial tools are available (EDIF, VHDL, Verilog, System C) Benefits for industry to be clarified and/or improved –Competence Centre of Mission Critical Embedded Systems (ELIKO) has been created (with contracts between 7 private companies, 2 res. institutions under leadership of TTU) –in this centre currently 2 test oriented joint projects with industry covering REASON WP3 topics are running

43. 3rd Annual Review Meeting, Sinaia, Romania, February 21-22, 2005 Main goals for 2005 AGBOT: Completing the Handbook on Testing Completing the development of research environment (incl. Educhip) –Development and update of a series of research scenarios –Special target: Hands-on lab courses for partners with partner tools –Testing the research scenarios A series of tutorials and courses planned: –Lecture course in Sweden, Febr-March –Tutorial at DDECS, April 18, Sopron –2 tutorials at European Test Symposion, May 21-25, Tallinn –1-day tutorial on VHDL, June, Liberec –Special session on Educhips at MIXDES –Other hands-on training sessions WP3 Workshop, May 20, Tallinn

44. 3rd Annual Review Meeting, Sinaia, Romania, February 21-22, 2005 Intensive cooperation has been the target, local actions were less important –Joint courses, tutorials and tool environments –Joint research scenarios –Joint work on the textbook: AGBOT –Joint research – 12 joint publications (side effect) Visibility of the WP3 team at the European level is increased Conclusions