1. Lecture 9 RTL Design Methodology Sorting Example

2. 2ECE 448 – FPGA and ASIC Design with VHDL Required reading S. Brown and Z. Vranesic, Fundamentals of Digital Logic with VHDL Design Chapter 10.2, Design Examples P. Chu, FPGA Prototyping by VHDL Examples Chapter 6, FSMD

3. Structure of a Typical Digital System Datapath (Execution Unit) Controller (Control Unit) Data Inputs Data Outputs Control & Status Inputs Control & Status Outputs Control Signals Status Signals

4. Hardware Design with RTL VHDL Pseudocode DatapathController Block diagram Block diagram State diagram or ASM chart VHDL code Interface

5. Steps of the Design Process 1.Text description 2.Interface 3.Pseudocode 4.Block diagram of the Datapath 5.Interface with the division into the Datapath and the Controller 6.ASM chart of the Controller 7.RTL VHDL code of the Datapath, the Controller, and the Top Unit 8.Testbench of the Datapath, the Controller, and the Top Unit 9.Functional simulation and debugging 10.Synthesis and post-synthesis simulation 11.Implementation and timing simulation 12.Experimental testing

6. Steps of the Design Process Practiced in Class Today 1.Text description 2.Interface 3.Pseudocode 4.Block diagram of the Datapath 5.Interface with the division into the Datapath and the Controller 6.ASM chart of the Controller 7.RTL VHDL code of the Datapath, the Controller, and the Top Unit 8.Testbench of the Datapath, the Controller, and the Top Unit 9.Functional simulation and debugging 10.Synthesis and post-synthesis simulation 11.Implementation and timing simulation 12.Experimental testing

7. Sorting example

8. Sorting - Required Interface Sorting Clock Resetn DataIn N DataOut N Done RAdd L WrInit S (0=initialization 1=computations) Rd

9. Sorting - Required Interface

10. Simulation results for the sort operation (1) Loading memory and starting sorting

11. Simulation results for the sort operation (2) Completing sorting and reading out memory

12. Before sorting During Sorting After sorting Address 01230123 3322111122333322444444431111223433221111223333224444444311112234 i=0i=0i=0i=1i=1i=2 j=1j=2j=3j=2j=3j=3 MiMi MjMj Legend: position of memory indexed by i position of memory indexed by j Sorting - Example

13. Pseudocode for i=0 to k2 do A= ; for j=i+1 to k1 do B=MjMj ; if B<A then MiMi =B ; MjMj =A ; A=MiMi ; endif; endfor; – - [load input data] [read output data] for i=0 to 2 do A= MiMi ; for j=i+1 to 3 do B=MjMj ; if B<A then MiMi =B ; MjMj =A ; A=MiMi ; endif; endfor; [load input data] [read output data] FOR k = 4FOR any k ≥ 2 MiMi

14. Pseudocode wait for s=1 for i=0 to k-2 do A = M i for j=i+1 to k-1 do B = M j if A > B then M i = B M j = A A = M i end if end for Done wait for s=0 go to the beginning

15. DIN DOUT ADDR WE CLK EN CLK RST EN CLK RST A>B 01 s WrInit Clock Resetn Wr 1 0 Bout EA EB AgtB Addr s 0 1 0 1 DataInRAdd Rd DataOut Csel EN CLK LD RST Resetn EN CLK LD RST Resetn Li Ei Clock Lj Ej Clock = k-2 = k-1 zi zj N L L L L N N N N N ABMux A B i j Mij Din We 0 L +1 Block diagram of the Datapath

16. N ClockResetn DataOut N WrInits Done Wr Li Ei Lj Ej EA EB Bout Csel DatapathController RAddr L zi Interface with the division into the Datapath and the Controller DataIn Rd AgtB zj