1. ECE 875: Electronic Devices Prof. Virginia Ayres Electrical & Computer Engineering Michigan State University ayresv@msu.edu

2. VM Ayres, ECE875, S14 Lecture 36, 09 Apr 14 Chp 06: MOSFETs Aspects of realistic MOSFET operation (n-channel p-substrate) Comment on 2D mobility  Use of field oxide in CMOS Short channel effects on ON operation: high E (y) => velocity saturation => lower I DS micron-scale = worst nano-scale = not so bad scaling Good test for future ON/OFF operation: sub-threshold (not fully ON) swing

3. IDID In the charge sheet and constant mobility approximation: VM Ayres, ECE875, S14 Mobility is assumed to be constant However: It is a different value than 3D bulk mobility

4. VM Ayres, ECE875, S14 Lecture 36, 09 Apr 14 Chp 06: MOSFETs Aspects of realistic MOSFET operation (n-channel p-substrate) Comment on 2D mobility  Use of field oxide in CMOS Short channel effects on ON operation: high E (y) => velocity saturation => lower I DS micron-scale = worst nano-scale = not so bad scaling Good test for future ON/OFF operation: sub-threshold (not fully ON) swing

5. Use CMOS (complementary metal-oxide-semiconductor FET) or NMOS design to reduce power consumption. + -

6. Use CMOS (complementary metal-oxide-semiconductor FET) or NMOS design to reduce power consumption. + - Wikipedia - A high voltage on the gates will cause the nMOSFET to conduct and the pMOSFET to not conduct while a low voltage on the gates causes the reverse. This arrangement greatly reduces power consumption and heat generation. However, during the switching time both MOSFETs conduct briefly as the gate voltage goes from one state to another. This induces a brief spike in power consumption and becomes a serious issue at high frequencies. VM Ayres, ECE875, S14

7. Another issue: Coulomb forces are distance dependent and spatially they last forever. So charges on a 1st gate can influence the channel under the 2nd gate. + - VM Ayres, ECE875, S14

8. Block with an oxide called the “field oxide” = more SiO 2 : + - VM Ayres, ECE875, S14

9. - + OFF CMOS: -+ ON VM Ayres, ECE875, S14

10. IDID Working tools: Linear, saturation and intermediate forms Channel/ Drain to Source Potential associated with E-field across oxide: VM Ayres, ECE875, S14

11. Given: both gates are n+ poly Si, which acts like a metal -0.98 V 1 st term in V FB : VM Ayres, ECE875, S14

12. Q insulator = Q m + Q ot + Q f + Q it Given: Q f /q = 10 11 Assume: Q m = Q ot = Q it = 0 for this insulator under these operating conditions Therefore: Q insulator = 10 11 x 1.6 x 10 -19 C And: 2 nd term in V FB : VM Ayres, ECE875, S14

13. Next term: 2  B : VM Ayres, ECE875, S14

14. Next term: Q D /C ox : VM Ayres, ECE875, S14

15. Goal: want minimum isolation V T = 20 V VM Ayres, ECE875, S14

16. Goal: want minimum isolation V T = 20 V Set = VM Ayres, ECE875, S14

17. Lecture 36, 09 Apr 14 Chp 06: MOSFETs Aspects of realistic MOSFET operation (n-channel p-substrate) Comment on 2D mobility  Use of field oxide in CMOS Short channel effects on ON operation: high E (y) => velocity saturation => lower I DS micron-scale = worst nano-scale = not so bad scaling Good test for future ON/OFF operation: sub-threshold (not fully ON) swing

18. Goal: More MOSFETs/CMOSs = more computer capability. Therefore make each MOSFET /CMOS smaller. Current CMOS: 22 nm node. Node VM Ayres, ECE875, S14

19. Problem: make channel length L shorter and MOSFET device performance deteriorates (see RHS). Why is this? Small L = “short channel” VM Ayres, ECE875, S14

20. IDID Linear, saturation and intermediate forms Charge sheet + constant mobility approximation Problem is with mobility/velocity: Constant mobility assumption: =  E (y) VM Ayres, ECE875, S14

21. E  VM Ayres, ECE875, S14

22. Problem is with mobility/velocity: We assumed that =  E (y) meant a linear function of E (y). This is only true for low V DS (low bias). Realistically: VM Ayres, ECE875, S14

23. Problem is with mobility/velocity: ECE 474: “velocity saturation”: E ext 10 5 V/cm E (y) that increases along L VM Ayres, ECE875, S14

24. At high E (y)-field near Drain, have a velocity saturation effect that has nothing to do with pinch in the channel. E (y) that increases along L VM Ayres, ECE875, S14

25. Result of velocity saturation: RHS: Small L = “short channel” velocity saturation occurs at lower V DS than that required for the channel pinch due to development of the depletion regions at the Drain end High E -field in channel  large V DS drop across a physically small L VM Ayres, ECE875, S14

26. What to use for mobility  now: E (y) that increases along L n = 2  empirical velocity saturation of electrons in Si channel for moderate doping VM Ayres, ECE875, S14

27. What to use for mobility  now: E (y) that increases along L n = 1  empirical holes in Si channel for moderate doping n = 1 is also a mathematically simpler approximation for the n = 2 curve for electrons VM Ayres, ECE875, S14

28. What to use for mobility  now: E (y) that increases along L Two straight lines and avoid the point where they cross is another simpler approximation for the n = 2 curve for electrons VM Ayres, ECE875, S14