1. Logic Synthesis for Low Power(CHAPTER 6) 6.1 Introduction 6.2 Power Estimation Techniques 6.3 Power Minimization Techniques 6.4 Summary

2. 6.1 Introduction[1] Low power, yet high-throughput and computationally intensive circuits are becoming a critical application domainLow power, yet high-throughput and computationally intensive circuits are becoming a critical application domain 1) One driving factor 1) One driving factor - Growing class of personal computing devices and wireless - Growing class of personal computing devices and wireless communications systems communications systems -> demand high-speed computations and comlex functionalilies -> demand high-speed computations and comlex functionalilies with low power comsumption with low power comsumption 2) Another crucial driving factor 2) Another crucial driving factor - Excessive power consumption in intergrating more transistors - Excessive power consumption in intergrating more transistors on a single chip or on a multiple-chip module on a single chip or on a multiple-chip module

3. 6.1 Introduction[2] - Unless power consumption is dramatically reduced, the - Unless power consumption is dramatically reduced, the resulting heat limits the feasible packing and performance resulting heat limits the feasible packing and performance of VLSI circuits and systems of VLSI circuits and systems - Circuits synthesized for low power are less susceptible to - Circuits synthesized for low power are less susceptible to run time failures run time failures

4. 6.1 Introduction[3] Multifaceted approach attaking the problem on four frontsMultifaceted approach attaking the problem on four fronts 1) Reducing chip and package capacitance 1) Reducing chip and package capacitance - Process development such as SOI(Silicon On Insulator) with - Process development such as SOI(Silicon On Insulator) with fully depleted wells, process scaling to submicron device fully depleted wells, process scaling to submicron device sizes, and advanced inerconnect substrates such as Multi-Chip sizes, and advanced inerconnect substrates such as Multi-Chip module module 2) Scaling the supply voltage 2) Scaling the supply voltage - Require new IC fabrication processing - Require new IC fabrication processing - Require support circuitry for low-voltage operation including - Require support circuitry for low-voltage operation including level-converters and DC/DC converters level-converters and DC/DC converters

5. 6.1 Introduction[4 ] 3) Using power management strategies 3) Using power management strategies - Various static and dynamic power management techniques - Various static and dynamic power management techniques - Very application dependent - Very application dependent 4) Employing better design techniques 4) Employing better design techniques - Investment to reduce power by design is relatively small in - Investment to reduce power by design is relatively small in comparision to the other two approaches comparision to the other two approaches

6. 6.1 Introduction[5 ] System LevelSystem Level - Inactive hardware module may be automatically turned off - Inactive hardware module may be automatically turned off - Module provided with the optimum supply voltage and interfaced - Module provided with the optimum supply voltage and interfaced by means of level converters by means of level converters - Some of energy cycled back to the power supply - Some of energy cycled back to the power supply - Task partitioned between various hardware modules or programmable - Task partitioned between various hardware modules or programmable processors processors

7. 6.1 Introduction[6] Architectural(behavioral) design levelArchitectural(behavioral) design level - Concurrency increasing transformation - Concurrency increasing transformation -> loop unrolling, pipeling, control flow optimization -> loop unrolling, pipeling, control flow optimization - Critical path reducing transformation - Critical path reducing transformation -> height minimization, retiming, pipeling -> height minimization, retiming, pipeling - Algorithm-specific instruction set may be utilized - Algorithm-specific instruction set may be utilized -> boost code density and minimize switching -> boost code density and minimize switching - Gray code addressing scheme - Gray code addressing scheme -> reduce the number of bit change -> reduce the number of bit change - On-chip cache -> minimize external memory references - On-chip cache -> minimize external memory references - Locality -> avoid accessing global resources - Locality -> avoid accessing global resources

8. 6.1 Introduction[7] Register-transfer and logic levelRegister-transfer and logic level - Symbolic states of a FSM can be assigned binary codes to - Symbolic states of a FSM can be assigned binary codes to minimize the number of bit changes minimize the number of bit changes - Latches in a piplined design can be repositioned - Latches in a piplined design can be repositioned -> eliminate hazardous activity in the circuit -> eliminate hazardous activity in the circuit - Output logic values of a circuit precomputed one cycle before - Output logic values of a circuit precomputed one cycle before - Common sub-expressions with low transition extracted - Common sub-expressions with low transition extracted - Nodes with high switching activity hidden inside CMOS - Nodes with high switching activity hidden inside CMOS - Gate resizing, signal-to-pin assignment, I/O encoding - Gate resizing, signal-to-pin assignment, I/O encoding

9. 6.1 Introduction[8] Physical design levelPhysical design level - Use appropriate net weights during - Use appropriate net weights during -> netlist partitioning, floorplanning, placement, routing -> netlist partitioning, floorplanning, placement, routing - Individual transistors sized down - Individual transistors sized down - Use optimally sized inverter chains - Use optimally sized inverter chains -> buffer large capacitive loads -> buffer large capacitive loads - Combine wire and driver sizing - Combine wire and driver sizing -> reduce the interconnect delay -> reduce the interconnect delay -> small increase in the power dissipation -> small increase in the power dissipation - Clock tree - Clock tree -> minimize the load on the clock drivers -> minimize the load on the clock drivers

10. 6.1 Introduction[9] Circuit levelCircuit level - Recycle the signal energies using the adiabatic switching - Recycle the signal energies using the adiabatic switching principles principles - Conbine self-timed circuits with a mechanism for selective - Conbine self-timed circuits with a mechanism for selective adjustment of the supply voltage adjustment of the supply voltage - Transfer of the energy stored on a capacitance to some charge - Transfer of the energy stored on a capacitance to some charge sharing capacitances sharing capacitances - Design energy efficient level-converters - Design energy efficient level-converters - DC/DC converters - DC/DC converters

11. 6.1 Introduction[10] Design for low power problem can be achieved withDesign for low power problem can be achieved with - Accurate power prediction and optimization tools - Accurate power prediction and optimization tools - Power efficient gate and module libraries - Power efficient gate and module libraries Critical need for CAD toolsCritical need for CAD tools 1) to estimate power dissipation during design process to meet 1) to estimate power dissipation during design process to meet the power budget the power budget 2) to enable efficient design and characterization of the design 2) to enable efficient design and characterization of the design libraries libraries 3) to reduce the power dissipation using various transformation 3) to reduce the power dissipation using various transformation and optimizatons and optimizatons

12. 6.2 Power Estimation Techniques Multifaceted approach attaking the problem on four frontsMultifaceted approach attaking the problem on four fronts 1) Reducing chip and package capacitance 1) Reducing chip and package capacitance - Process development such as SOI(Silicon On Insulator) with - Process development such as SOI(Silicon On Insulator) with fully depleted wells, process scaling to submicron device fully depleted wells, process scaling to submicron device sizes, and advanced inerconnect substrates such as Multi-Chip sizes, and advanced inerconnect substrates such as Multi-Chip module module 2) Scaling the supply voltage 2) Scaling the supply voltage - Require new IC fabrication processing - Require new IC fabrication processing - Require support circuitry for low-voltage operation including - Require support circuitry for low-voltage operation including level-converters and DC/DC converters level-converters and DC/DC converters