1. Modern VLSI Design 4e: Chapter 2 Copyright  2009 Prentice Hall PTR Topics n Basic fabrication steps. n Transistor structures. n Basic transistor behavior. n Latch up.

2. Modern VLSI Design 4e: Chapter 2 Copyright  2009 Prentice Hall PTR Our technology n We will study a generic 180 nm technology. –Assume 1.2V supply voltage. n Parameters are typical values. n Parameter sets/Spice models are often available for 180 nm, harder to find for 90 nm.

3. Modern VLSI Design 4e: Chapter 2 Copyright  2009 Prentice Hall PTR Fabrication services n Educational services: –U.S.: MOSIS –EC: EuroPractice –Taiwan: CIC –Japan: VDEC n Foundry = fabrication line for hire. –Foundries are major source of fab capacity today.

4. Modern VLSI Design 4e: Chapter 2 Copyright  2009 Prentice Hall PTR Fabrication processes n IC built on silicon substrate: –some structures diffused into substrate; – other structures built on top of substrate. n Substrate regions are doped with n-type and p-type impurities. (n+ = heavily doped) n Wires made of polycrystalline silicon (poly), multiple layers of aluminum (metal). n Silicon dioxide (SiO 2 ) is insulator.

5. Modern VLSI Design 4e: Chapter 2 Copyright  2009 Prentice Hall PTR Simple cross section substrate n+ p+ substrate metal1 poly SiO 2 metal2 metal3 transistor via

6. Modern VLSI Design 4e: Chapter 2 Copyright  2009 Prentice Hall PTR Photolithography Mask patterns are put on wafer using photo- sensitive material:

7. Modern VLSI Design 4e: Chapter 2 Copyright  2009 Prentice Hall PTR Process steps First place tubs to provide properly-doped substrate for n-type, p-type transistors: p-tub substrate

8. Modern VLSI Design 4e: Chapter 2 Copyright  2009 Prentice Hall PTR Process steps, cont’d. Pattern polysilicon before diffusion regions: p-tub poly gate oxide

9. Modern VLSI Design 4e: Chapter 2 Copyright  2009 Prentice Hall PTR Process steps, cont’d Add diffusions, performing self-masking: p-tub poly n+ p+

10. Modern VLSI Design 4e: Chapter 2 Copyright  2009 Prentice Hall PTR Process steps, cont’d Start adding metal layers: p-tub poly n+ p+ metal 1 vias

11. Modern VLSI Design 4e: Chapter 2 Copyright  2009 Prentice Hall PTR Transistor structure n-type transistor:

12. Modern VLSI Design 4e: Chapter 2 Copyright  2009 Prentice Hall PTR 0.25 micron transistor (Bell Labs) poly silicide source/drain gate oxide

13. Modern VLSI Design 4e: Chapter 2 Copyright  2009 Prentice Hall PTR Transistor layout n-type (tubs may vary): w L

14. Modern VLSI Design 4e: Chapter 2 Copyright  2009 Prentice Hall PTR Drain current characteristics

15. Modern VLSI Design 4e: Chapter 2 Copyright  2009 Prentice Hall PTR Drain current n Linear region (V ds < V gs - V t ): –I d = k’ (W/L)(V gs - V t )(V ds - 0.5 V ds 2 ) n Saturation region (V ds >= V gs - V t ): –I d = 0.5k’ (W/L)(V gs - V t ) 2

16. Modern VLSI Design 4e: Chapter 2 Copyright  2009 Prentice Hall PTR 180 nm transconductances Typical values: n n-type: –k n ’ = 170  A/V 2 –V tn = 0.5 V n p-type: –k p ’ = 30  A/V 2 –V tp = -0.5 V

17. Modern VLSI Design 4e: Chapter 2 Copyright  2009 Prentice Hall PTR Current through a transistor Use 180 nm parameters. Let W/L = 3/2. Measure at boundary between linear and saturation regions. n V gs = 0.7V: I d = 0.5k’(W/L)(V gs -V t ) 2 = 5.3  A n V gs = 1.2V: I d = 62  A

18. Modern VLSI Design 4e: Chapter 2 Copyright  2009 Prentice Hall PTR Basic transistor parasitics n Gate to substrate, also gate to source/drain. n Source/drain capacitance, resistance.

19. Modern VLSI Design 4e: Chapter 2 Copyright  2009 Prentice Hall PTR Basic transistor parasitics, cont’d n Gate capacitance C g. Determined by active area. n Source/drain overlap capacitances C gs, C gd. Determined by source/gate and drain/gate overlaps. Independent of transistor L. –C gs = C ol W n Gate/bulk overlap capacitance.

20. Modern VLSI Design 4e: Chapter 2 Copyright  2009 Prentice Hall PTR Latch-up n CMOS ICs have parastic silicon-controlled rectifiers (SCRs). n When powered up, SCRs can turn on, creating low-resistance path from power to ground. Current can destroy chip. n Early CMOS problem. Can be solved with proper circuit/layout structures.

21. Modern VLSI Design 4e: Chapter 2 Copyright  2009 Prentice Hall PTR Parasitic SCR circuitI-V behavior

22. Modern VLSI Design 4e: Chapter 2 Copyright  2009 Prentice Hall PTR Parasitic SCR structure

23. Modern VLSI Design 4e: Chapter 2 Copyright  2009 Prentice Hall PTR Solution to latch-up Use tub ties to connect tub to power rail. Use enough to create low-voltage connection.

24. Modern VLSI Design 4e: Chapter 2 Copyright  2009 Prentice Hall PTR Tub tie layout metal (V DD ) p-tub p+