1. Nano Technology and Science
Metrology and Characterization Requirements and Challenges for the Nano-World of Integrated Circuits
And
Its Overlap with
Nano Technology and Science
Alain C. Diebold

2. AGENDA The ITRS Challenge Litho Metrology FEP & Interconnect Metrology
Materials Characterization

3. ITRS: International Technology Roadmap for Semiconductors
The ITRS includes the roadmap for emerging NanoTechnology and Electronics.
The ITRS is sponsored by the Semiconductor Industry Association (SIA), the European Electronic Component Association (EECA), the Japan Electronics & Information Technology Industries Association (JEITA), the Korean Semiconductor Industry Association (KSIA), and Taiwan Semiconductor Industry Association (TSIA)
International SEMATECH is the global communication center for this activity. The ITRS team also coordinates the USA region events.

4. ITRS Challenge for Metrology In-Time Metrology and Characterization
Describe what each line means.
Technology Nodes defined by DRAM ½ pitch
Logic gate length (isolated feature easier to pattern than dense feature) smaller than DRAM ½ pitch
DRAM at 65 nm node is 1 Gig 8 Gig at 22 nm node
Remember to state that tool suppliers, IC manufacturers, and development organizations (for example universities) need to work together. IC manufacturers need to provide ~20 nm features to these organizations. This needs encouragement.
Leading Edge Tool
Specifications set
32 nm Node Metrology R&D
Materials available
10 nm structures
difficult to obtain

5. ITRS Challenge New Materials and Structures
Describe what each line means.
Technology Nodes defined by DRAM ½ pitch
Logic gate length (isolated feature easier to pattern than dense feature) smaller than DRAM ½ pitch
DRAM at 65 nm node is 1 Gig 8 Gig at 22 nm node
Remember to state that tool suppliers, IC manufacturers, and development organizations (for example universities) need to work together. IC manufacturers need to provide ~20 nm features to these organizations. This needs encouragement.

6. Is based on Statistical Significance
Process control
Is based on Statistical Significance
CP = CPK
CP < 1
CP = 1
CP > 1 UL LL 6
If Distribution is Centered

7. Distribution of linewidths inside test structure
What are you Measuring?
single value from distribution of > 500 Million
average
test structure inside a die
Distribution of linewidths inside test structure

8. One Aspect of the Solution: Average over large area &
Amplify Signal from Microscopic Changes
e.g.
150 nm lines
300 nm pitch S L
Optical CD using Overlay System
Rapid Sampling of test structures

9. Components of Solution
SENSOR based Integrated Metrology Advanced Process Control - Advanced Equipment Control
Components of Solution
APC, including Run-to-run control
FDC: Fault Detection and Classification
Integrated Metrology
The monopole RGA sold by Ferran is also a MEMS
sensor. MEMS is more than silicon based
miniaturization
Mini-SEMs have are in the demonstration
of feasibility stage.
NIST has done some work in the area of MEMS
test structures for interconnect stress (these
structures would be placed in scribe areas of the wafer)

10. Metrology & New Structures
Memory
Logic

11. Messages from IC Industry
In-Line Metrology must be linked to the Manufacturing Process
Advanced Process Control and Advanced Equipment Control will be Necessary for NanoManufacturing Process Productivity
Metrology for NanoElectronics will also be more than Dimensional and Mechanical Measurements – Electrical Properties of materials and Electrical Parametrics of devices must be considered

12. AGENDA How to control microscopic features Litho Metrology
Example of Interaction between Manufacturing Process and Metrology
FEP & Interconnect Metrology
Materials Characterization

13. Litho Metrology for Volume Manufacturing
13 nm printed line width
9 nm physical line width
52 nm mask line width
26 nm scattering bars
22 nm Node
CD Control Starts at the Mask
152mm
6.35mm
Overlay and CD Control after Exposure
EUV
CD Control after Etch
Metrology starts with understanding of the process tools
Transistor gate length must fall with in a range of values. If the CD’s are within this range, the gate delay will be the same for all the transistors provided other processes such as implant dose are identical. This is a part of keeping the circuit operating at the highest clock speed.

14. Investigate High Voltage CD-SEM
100 – 200 keV e-
Comparison of conventional SE (left) and Low Loss (right) images of copper interconnects. Note the greatly enhanced surface detail and lack of edge brightness in the Low Loss image.
Low loss detector
Micrograph courtesy of O C Wells
Figures from David Joy

15. Scatterometry for CD Measurements What are the Limits
Polarization
Sensitive
Detector
Incident Polarized
White Light
0th order
Multi-wavelength
Light Source
Mirror
Q in =  out
Real Time Calculation
of line width & shape
Eliminates Libraries
Rigorous coupled wave theory (RCWT) is simply a mathematical mechanism that allows for the direct solution of the electromagnetic fields diffracted by a grating
1. Incident Region
2. Grating
3. Planar Layers
4. Substrate +z x y

16. Average vs Individual CD-SEM measures one line at a time
Scatterometry gives an average over many lines
Reports indicate a large number (80 different lines) CD-SEM measurements in test area required to match scatterometry average
Lose individual line information

17. CD Metrology: Status of scatterometry
Scatterometry works well for gate control
Ring Oscillators still (always will be?) key way to access CD control.
Closed Loop APC + scatterometry have resulted in a tightening of range of Idsat for microprocessors.
Tight Idsat gives tight distribution of Transistor Delay t
t ~ C Vdd/(Ion*W)
Ion units: µA/µm
C = Cs/d + CL
Out CL In
Vdd
Thanks to Peter Zeitzoff and Larry Larson

18. Opportunities for the distant future
Electron Holography & Low Energy Electron Microscopy (LEEM)
WHY HOLOGRAPHY?
Why low beam energies?
To minimize artifacts due to beam penetration, to minimize energy deposition and hence radiation damage in buried oxide layers, to reduce charging
But
The performance of low energy SEMs is limited by chromatic aberration, and diffraction effects, in the probe forming lens to a spatial resolution that is not adequate to achieve the performance required for micron design rule devices.
A solution
Use a nanotip field emitter, operating at 100 volts or so. This emits a highly coherent electron beam which is scattered and reflected from a patch micrometers in size on the surface of the device. The unscattered and scattered waves interfere to produce a hologram in the region downstream of the tip. A step and repeat technique is used to observe the complete specimen area.
Advantages
This instrument uses no lenses so it has neither aberration nor diffraction limitations. The resolution is limited by the electron wavelength. The electron beam is divergent so the beam dose rate is low, minimizing charging, contamination, and radiation damage.
Special benefits
All features in the illuminated patch contribute to the hologram, so the repeat spacings (in both the horizontal and vertical planes) that are determined from the hologram yield a statistical analysis of the entire area simultaneously. The hologram is self calibrating because the fringe spacing is only a function of the electron energy. No high speed scanning is required so the bandwidth and slew rate limiting artifacts characteristic of conventional e beam tools are absent.
Historical Note
This idea was first conceptualized by Russ Young (the guy who really invented the scanning tunneling microscope) at NBS in the 1970s. It was re discovered and demonstrated by Fink (IBK Zurich) in the 1980s and by Spence (ASU).
Other Uses?
(1) The hologram could be compared with a standard test hologram to yield an interferogram. which identified all regions not identical with the standard. It might thus be suitable for defect review.
(2) By placing "electron mirrors in the ray path interference patterns of arbitrary form can be produced at the sample. This spatial modulation of the beam intensity can be used for example for resistless lithography. No mask is required, and the low beam energy ensures a high rate of exposure at the surface.
David Joy
Point Projection
Microscope
LEEM
Si(111)
New normal incidence
David Joy, Univ. of TN
Tromp and Reuter IBM

19. AGENDA How to control microscopic features Litho Metrology
FEP & Interconnect Metrology
Materials Characterization

20. or locally strained channels
Front End Process & Interconnect Metrology
New Materials & Structures
Metal Gate
Strained Si & SOI
or locally strained channels
High 
& interfaces
CMOS and non-Classical CMOS

21. Interconnect Metrology
VOID Detection in Copper lines
Killer Pore Detection in Low k
Barrier / Seed Cu on sidewalls
Control of each new Low k

22. Quantum confinement for sub 20 nm silicon Need SOI Optical Constants
Extra reflection from SOI Wafers Impacts Optical Measurements and Light Scattering
Quantum confinement for sub 20 nm silicon
Need SOI Optical Constants

23. Quantum confinement effect on optical properties of very thin SOI
“bulk”

24. Beyond Classical CMOS Metrology on Sidewalls New Optical paths???
Double-Gate MOSFET

25. X-ray Reflectivity Angle Reflectivity Monochromator X-Ray Sensor
X-Ray Tube
Thin-Film Sample
Monochromator
Spatially Resolving
X-Ray Sensor
0.0001
0.001
0.01
0.1 1
0.0
0.5
1.0
1.5
Fit from SB-Code
Angle
Reflectivity
250Å ±1Å Ta
969ű1ŠCu
Silicon
16ű2Šrms
5ű1Šrms

26. AGENDA How to control microscopic features Litho Metrology
FEP & Interconnect Metrology
Materials Characterization

27. Materials Characterization NEEDS
Atomic Resolution including Interface Analysis
Rapid Sample Preparation and Analysis
Move new Materials Characterization into Manufacturing as soon as possible
Location of NanoFeatures to allow Characterization – e.g. Dual Column FIB
Optical Metrology is part of total picture of Off-line Characterization
Trace Analysis Improvements

28. The future : Aberration Correction Lens for TEM/STEM
The next step in improving spatial resolution for HR-TEM and ADF-STEM
Phil Batson’s demonstration of sub – Angstrom resolution for STEM
Commercial TEM’s with aberration correction lens now available.
Next generation TEM - TEAM project is critical to Nanotechnology
TEAM = transmission electron aberration corrected microscope

29. Aberration Correction LENS for TEM Also Improves Spatial Resolution for ELS

30. Professor John Sinclair Cornell

31. SEM with Aberration Correction LENs
Commercial SEM with aberration corrections now available
What are pros and cons of use in SEM?

32. Local Electrode Atom Probe
Vaccel z
Vpulseb y x
Vex
Atom Distribution
: < 100% detection
Tom Kelly - Imago

33. LEAP – Next Steps
Develop Infrastructure in Universities and National Labs
Develop Applications
Improve Detection to ~100%
What to do about insulators??

34. Conclusions
Semiconductor Industry is already Roadmapping the 15 year horizon for NanoElectronics.
NanoElectronic Research already requires characterization with atomic resolution
Economically feasible NanoElectronic Manufacturing requires rapid, statistically significant Metrology
US centric TEM [TEAM] project is critical to NanoTechnology

35. Extra Overheads

36. Length or CD Width Current flow p-Si core/i-Ge/SiOx/p-Ge GL = 1500 nm
EOT ~ 0.4nm
Observed range of 1 to 5  1V
Diameter without metal connection to Ge gate is 50 nm
Length or CD
Width
Current
flow
1 milli-amp of current/ m needed to meet performance requirements
1 x 10-3 amps = 200 nanowire transistors x 5000 nano Amps/transistor
This would require 200 nanowires in 1 micron width = 50 nm / nanowire
with Idsat = ~ 5 A/m of each nanowire 1Vdd Or
1000 nano Amps/transistor x 1000 nanowire transistors with 10 nm space
With Idsat = ~ 1 A/m an impossible pitch

37. SEM for CD Measurements
Top Down
Image

38. Ultra-Low Voltage CD-SEM - Line Edge Determination (Still) requires a model
Figure courtesy Neil Sullivan

39. Metal Illumination Borden, Smith, Diebold, Chism,
IEEE Transactions on Semiconductor Manufacturing
16, August 2003

40. Metal Illumination: Detection of open vias
Borden, Smith, Diebold, Chism,
IEEE Transactions on Semiconductor Manufacturing
16, August 2003

41. R-C test structures of new low  Prior to manufacture
Resistance Test
Capacitance Test

42. Pores are Difficult to see!!!
Bryan Tracy AMD
Low k Cross-section Image from most advanced Lab SEM

43. XRR for low  process control
Porous Low-k
391.1 nm
SiNC 15 nm (density 1.89g/cm3)
SiNC 3 nm (density 1.70g/cm3)
SiO2 (density 2.14 g/cm3)
550 nm
18 nm
6 periods
Si substrate

44. Optical Models for Each New Low 

45. Pore Size Distribution Diffuse (small angle) x-ray scattering
Scattering Angle 2 4 6 8
Scattering Intensity
105
100 10 20 30 40 50 60 70
0.000
0.010
0.020
0.030
0.040
0.050
Average pore diameter = 50 Å
p = 0.2
p = 0.5
p = 1
r (Å)
(r) p

46. Pores Size Distribution via :
a Diffuse X-ray Scattering
b Ellipsometric Porosimetry 10 20 30 40 50 60 70
0.000
0.010
0.020
0.030
0.040
0.050
Average pore diameter = 50 Å
p = 0.2
p = 0.5
p = 1
r (Å)
dV/dR
(r) p a b

47. Impulsively Stimulated Thermal Scattering
Film
Substrate
Probe Beam
Detector
1 - Probe beam strikes surface
Cu 270 MHz
Excitation Laser Pulse
grating
Acoustic
Wavelength
2 - Form grating and excite acoustic wave
Diffracted
Reflected
Detector
3 - Probe beam diffracted as wave travels parallel to surface

49. SHG Experimental Setup- F i l t e r P r i s m R G - F i l t e r I r i s P o l a r i z e r s w 2 w @ 3 e V L e n s e s T i : S a p p h i r e L a s e r l = 7 - 9 2 n m , t = 1 f s , p P = 4 m W a v S a m p l e R o t a t i o n T a b l e 2 2 ( 2 w ) w c ( 2 ) + c ( 3 ) ( ) I ( t ) E ( t ) I
Norm Tolk - Vanderbilt University Mike Downer – University of Texas

50. Laser Stimulated Electron Injection
Example of leakage current measurements : Effect of X-Ray Induced Traps
Si SiO2 e-
Before Irradiation After Irradiation
Traps have two functions:
to trap electrons
to provide hopping centers for electron tunneling
Norm Tolk - Vanderbilt University

51. ε Coherent spin transport across GaAs/GaSb/InAs heterostructure
The thermalization and cooling of electrons and holes within ~ 1 ps result in a charge separation, thus creating interfacial electric fields
The resulting electric fields bend the initial band alignment and confine spins at the interfaces, thus creating interfacial magnetic fields
Spin-polarized electrons are excited in GaAs by 150-fs circularly polarized light
Due to coherent spin transport,
magnetization appears itself in InAs epilayer
Norm Tolk - Vanderbilt University

52. Spin Polarized Electrons
Band Offset Measurement : Motivation
Band offsets are crucial parameters in spin-carrier
dynamics and spin-polarized carrier transport across
semiconductor heterostructures. For many
semiconductor interfaces under investigation for
spintronics application these band offsets are
experimentally not well characterized.
The external magnetic field, the surface and bulk
states of the insulator, electrical and structural stress
and externally introduced damage all affect the
tunneling of spin carriers
Band offsets studies help us understand the photon-
energy dependent measurements of optically excited
spin carrier tunneling (Spin Leakage Currents)
through thin insulators through the band bending due
to charge redistribution.
Semiconductor
Spin Polarized Electrons
Thin
Insulator
Norm Tolk - Vanderbilt University

53. Band Offset Measurement Approaches
At Vanderbilt, we have successfully measured band offsets at semiconductor
interfaces using both IPE and SHG.
We are now in the process of applying these techniques to spin interesting materials.
Norm Tolk - Vanderbilt University

54. New Methods Detail in wafer Beam Excess carriers Junction
Generation laser
Probe laser
Beam splitter
Detector
Vision system
Objective lens
Detail in wafer
Junction
Beam
Excess carriers

55. Infrastructure for Ion Beam analysis
US National Labs have great Infrastructure
Don’t forget to use ion beam analysis for nano- technology
Numerous methods classified as Ion Beam
RBS
NRA
HIBS
MEIS
PIXIE
Etc.

56. Scanned Probe Microscopy

57. Advanced Optical Methods
Optical Second Harmonic Generation (SHG)
Spectroscopic determination of surface / interface dielectric function
Ultra-fast Optical Measurements
SHG using ultra-fast pump probe allows determination of carrier transport properties
Spin transport characterization
Band Offset Determination
Faraday Measurements for Spin Transport

58. Metrology & New Structures
Memory
Logic

59. Metrology & Molecular ElectronicsB C
Paul Weiss’s Group – STM of Conductance Switching

60. Nanowire Transistors and Interconnect
5 nm layer of Ge on top of
4 nm SiOx
10 nm p-Si core diameter
& 10 nm i- Ge layer
Figure 5 Coaxially-gated nanowire transistors. a, Device schematic showing transistor structure. The inset shows the cross-section of the as-grown nanowire, starting with a p-doped Si core (blue, 10 nm) with subsequent layers of i-Ge (red, 10 nm), SiOx (green, 4 nm), and p-Ge (5 nm). The source (S) and drain (D) electrodes are contacted to the inner i-Ge core, while the gate electrode (G) is in contact with the outer p-Ge shell and electrically isolated from the core by the SiOx layer. b, Scanning electron micrograph (SEM) of a coaxial transistor. Source and drain electrodes were deposited after etching the Ge (30% H2O2, 20 s) and SiOx layers (buffered HF, 10 s) to expose the core layers. The etching of these outer layers is shown clearly in the inset and is indicated by the arrow. The gate electrodes were defined in a second step without any etching before contact deposition. Scale bar is 500 nm. c, Gate response of the coaxial transistor at VSD = 1 V, showing a maximum transconductance of 1,500 nA V-1. Charge transfer from the p-Si core to the i-Ge shell produces a highly conductive and gateable channel.
500 nm
L.J. LAUHON, M.S. GUDIKSEN, D. WANG
& CHARLES M. LIEBER
Nature 420, (2002)