1. Penn ESE370 Fall2012 -- DeHon 1 ESE370: Circuit-Level Modeling, Design, and Optimization for Digital Systems Day 35: December 5, 2012 Transmission Lines Implications

2. Transmission Line Agenda Where arise? General wire formulation Lossless Transmission Line See in action in lab Impedance End of Transmission Line? Termination Implications Discuss Lossy Penn ESE370 Fall2012 -- DeHon 2

3. Transmission Line Data travels as waves Line has Impedance May reflect at end of line Penn ESE370 Fall2012 -- DeHon 3

4. Series Termination What happens here? Penn ESE370 Fall2012 -- DeHon 4

5. Simulation Penn ESE370 Fall2012 -- DeHon 5

6. Series Termination R series = Z 0 Initial voltage divider –Half voltage pulse down line End of line open circuit – sees single transition to full voltage Reflection returns to source and sees termination R series = Z 0 No further reflections Penn ESE370 Fall2012 -- DeHon 6

7. Termination Cases Parallel at Sink Series at Source Penn ESE370 Fall2012 -- DeHon 7

8. CMOS Driver / Receiver Driver: What does a CMOS driver look like at the source? –I d,sat =1200  A/  m @ 45nm Receiver: What does a CMOS inverter look like at the sink? Penn ESE370 Fall2012 -- DeHon 8

9. Some Transmission Lines Characteristics arise form their geometry Penn ESE370 Fall2012 -- DeHon 9

10. Coaxial Cable Inner core conductor: radius r Insulator: out to radius R Outer core shield (ground) RG-58 Z 0 = 50  – networking, lab (RG-59 Z 0 = 75  – video) Penn ESE370 Fall2012 -- DeHon 10

11. Printed Circuit Board Stripline –Trace between planes Penn ESE370 Fall2012 -- DeHon 11 w t b rr

12. Printed Circuit Board Microstrip line –Trace over single supply plane Penn ESE370 Fall2012 -- DeHon 12 w t h rr 00

13. Twisted Pair Category 5 ethernet cable –100  –V=0.64c 0 Penn ESE370 Fall2012 -- DeHon 13 Source: http://en.wikipedia.org/wiki/File:Cat_5.jpg

14. Termination Cases Parallel at Sink Series at Source Penn ESE370 Fall2012 -- DeHon 14 Either: destination sees source voltage after delay.

15. Example 25meter category-5e cable (100 , 0.64c) Supporting 1Gb/s ethernet –4 pairs at 250Mb/s Time to send data from one end to the other? Time between bits at 250Mb/s? Bits in the cable? Penn ESE370 Fall2012 -- DeHon 15

16. Pipeline Bits For properly terminated transmission line –Do not need to wait for bits to arrive at sink –Can stick new bits onto wire Penn ESE370 Fall2012 -- DeHon 16

17. Limits to Bit Pipelining What limits? (why only 250Mb/s) –Risetime/distortion –Clocking Skew Jitter –For bus Wire length differences between lines Penn ESE370 Fall2012 -- DeHon 17

18. Eye Diagrams Watch bits over line on scope –Look at distortion –“open” eye clean place to sample Consistent timing of transitions Well defined high/low voltage levels Penn ESE370 Fall2012 -- DeHon 18 http://en.wikipedia.org/wiki/File:On-off_keying_eye_diagram.svg http://focus.ti.com/analog/docs/gencontent.tsp?familyId=361&genContentId=41762&DCMP=ESD_Solutions&HQS=Other+OT+esd

19. Bad “eye” Penn ESE370 Fall2012 -- DeHon 19 http://archive.chipcenter.com/knowledge_centers/asic/todays_feature/showArticle.jhtml?articleID=12800254

20. Termination / Mismatch Wires do look like these transmission lines We are terminating them in some way when we connect to chip (gate) –Need to be deliberate about how terminate, if we care about high performance Penn ESE370 Fall2012 -- DeHon 20

21. Where Mismatch? Vias Wire corners? Branches Connectors Board-to-cable Cable-to-cable Penn ESE370 Fall2012 -- DeHon 21 http://wiki.altium.com/display/ADOH/An+Overview+of+Electronic+Product+Development+in+Altium+Designer http://www.fpga4fun.com/Hands-on_Flashy.html

22. Impedance Change What happens if there is an impedance change in the wire? Z 0 =75 , Z 1 =50  –What reflections and transmission do we get? Penn ESE370 Fall2012 -- DeHon 22

23. Z 0 =75, Z 1 =50 At junction: –Reflects V r =(50-75)/(50+75)V i –Transmits V t =(100/(50+75))V i Penn ESE370 Fall2012 -- DeHon 23

24. Impedance Change Z 0 =75, Z 1 =50 Penn ESE370 Fall2012 -- DeHon 24

25. Lossy Transmission Line How do addition of R’s change? –Concretely, discretely think about R=0.2  every meter on Z 0 =100  what does each R do? Penn ESE370 Fall2012 -- DeHon 25

26. Lossy Transmission Line R’s cause signal attenuation (loss) –Voltage divider R Z 0 –Reduced signal swing at sink –Limits length of transmission line before need to restore signal Penn ESE370 Fall2012 -- DeHon 26

27. What happens at branch? Penn ESE370 Fall2012 -- DeHon 27

28. Branch Transmission line sees two Z 0 in parallel –Looks like Z 0 /2 Penn ESE370 Fall2012 -- DeHon 28

29. Z 0 =50, Z 1 =25 At junction: –Reflects V r =(25-50)/(25+50)V i –Transmits V t =(50/(25+50))V i Penn ESE370 Fall2012 -- DeHon 29

30. End of Branch What happens at end? If ends in matched, parallel termination –No further reflections Penn ESE370 Fall2012 -- DeHon 30

31. Branch Simulation Penn ESE370 Fall2012 -- DeHon 31

32. Branch with Open Circuit? What happens if branch open circuit? Penn ESE370 Fall2012 -- DeHon 32

33. Branch with Open Circuit Reflects at end of open-circuit stub Reflection returns to branch –…and encounters branch again –Send transmission pulse to both Source and other branch Sink sees original pulse as multiple smaller pulses spread out over time Penn ESE370 Fall2012 -- DeHon 33

34. Open Branch Simulation Penn ESE370 Fall2012 -- DeHon 34

35. Open Branch Simulation Penn ESE370 Fall2012 -- DeHon 35

36. Bus Common to have many modules on a bus –E.g. PCI slots –DIMM slots for memory High speed  bus lines are trans. lines Penn ESE370 Fall2012 -- DeHon 36 http://en.wikipedia.org/wiki/File:DIMMs.jpg

37. Multi-drop Bus Ideal –Open circuit, no load Penn ESE370 Fall2012 -- DeHon 37

38. Multi-Drop Bus Impact of capacitive load (stub) at drop? –If tight/regular enough, change Z of line Penn ESE370 Fall2012 -- DeHon 38

39. Multi-Drop Bus Long wire stub? –Looks like branch may produce reflections Penn ESE370 Fall2012 -- DeHon 39

40. Transmission Line Noise Frequency limits Imperfect termination Mismatched segments/junctions/vias/connectors Loss due to resistance in line –Limits length Penn ESE370 Fall2012 -- DeHon 40

41. Idea Transmission lines –high-speed –high throughput –long-distance signaling Termination Signal quality Penn ESE370 Fall2012 -- DeHon 41

42. Admin HW7 due Thursday Last lecture Friday Final following Friday (12/14) –2011 final available to practice –2010 final up with solutions Good transmission line problem Problem 2 precharge logic (skipped this term) Ok crosstalk problem, memory problem –Review by Udit on Wed. 12/12 Penn ESE370 Fall2012 -- DeHon 42