1. Presenter : Ching-Hua Huang 2013/12/30 Finding Reset Nondeterminism in RTL Designs – Scalable X-Analysis Methodology and Case Study Cited count : 4 Hong-Zu Chou ; Haiqian Yu ; Kai-Hui Chang ; Dobbyn Dobbyn and Sy-Yen Kuo Electr. Eng. Dept., Nat. Taiwan Univ., Taipei, Taiwan 2010 Design, Automation & Test in Europe Conference & Exhibition (DATE), 2010 National Sun Yat-sen University Embedded System Laboratory

2. Due to increases in design complexity, routing a reset signal to all registers is becoming more difficult. One way to solve this problem is to reset only certain registers and rely on a software initialization sequence to reset other registers. This approach, however, may allow unknown values (also called X- values) in uninitialized registers to leak to other registers, leaving the design in a nondeterministic state. Although logic simulation can find some X-problems, it is not accurate and may miss bugs. A recent approach based on symbolic simulation can handle Xs accurately; however, it is not scalable. In this work we analyze the characteristics of X-problems and propose a methodology that leverages the accuracy of formal X-analysis and can scale to large designs. This is achieved by our novel partitioning techniques and the intelligent use of waveforms as stimulus. We applied our methodology to an industrial design and successfully identified several Xs unknown to the designers, including three real bugs, demonstrating the effectiveness of our approach. 2

3. 3  Logic simulation ◦ To predict the behavior of digital circuits and hardware description languages by the simulation software. ◦ Simulation can be performed at varying degrees of physical abstraction, such as at the transistor level, gate level, register-transfer level (RTL), electronic system-level (ESL), or behavioral level.  Symbolic simulation ◦ It is involves evaluating circuit behavior using special symbolic values to encode a range of circuit operating conditions. ◦ Simulator can be input symbols or variables and then propagates the Boolean expressions. Logic simulationSymbolic simulation

4. 4 What’s the problem  Some registers that be used to hold intermediate values in an arithmetic unit, may even be left uninitialized. ◦ If those Xs are not handled correctly, they may leak to important registers and leave the design in a nondeterministic state, causing serious problems.  In order to resolve the Xs easily, engineers are desirable to find and fix all Xs in RTL design. ◦ Resolve approach :  (1) To set uninitialized registers and perform logic simulation to check.  (2) Run gate-level simulation and compare result with RTL simulation. ◦ Problem :  (1) Although this way is fast and easy to implement, but the result is often inaccurate due to X-optimism and X-pessimism in logic simulation.  (2) Gate-level simulation is much slower. Furthermore, once a bug is found, identifying the root cause of the problem in the RTL code may be challenging.

5. 5 [2,10] The kind of X- problems [2,10] The kind of X- problems [This paper] [8] SAT-based method [8] SAT-based method [6] Ad-Hoc Translations [6] Ad-Hoc Translations Xs can enabling synthesis tools to perform better optimizations Using symbolic simulation and SAT solvers to find X- problems at the RTL Chou’s [5] Identifying the root cause Chou’s [5] Identifying the root cause [3,10] X-related problems [3,10] X-related problems Computing reset sequences that can be utilized to prevent undesirable X propagations Routing the reset signal to all registers is becoming more difficult [9] Global Routing [9] Global Routing [4] Bridging RTL and Gate [4] Bridging RTL and Gate Identifying the root cause of the problem in the RTL code may be challenging A technique that utilizes automatic RTL code transformation to avoid unexpected X- propagation. X-handling in logic simulation is often inaccurate due to X- optimism and X- pessimism

6. 6  In order to devise practical solutions for the X-problem, this paper performed an analytical study on X-problems in RTL designs.  X-problems have the following characteristics ◦ Xs is often localized and can be traced back to just an if-then block or a case statement  Challenge : Can be easily masked ◦ Xs propagate out and affect many other registers  Challenge : Finding root cause ◦ Xs are allowed after initialization  Challenge : What to check

7. 7  Analyzed the characteristics of X-problems and proposed an novel methodology called “eXact”. ◦ Adopted Chou’s formal X-analysis method due to its accuracy ◦ Applied several partitioning techniques to increase its scalability  An approach that only reports X-problems missed by logic simulation ◦ This approach can reduce X-analysis effort and let designers focus on real problems

8. 8  Goal : Design a practical methodology that can find X- problems in industrial-size circuits. ◦ Fit in the simulation-based verification flow ◦ Must scale to large designs  Problem formulation ◦ The rest of the bugs are those masked by logic simulation due to X-optimism. ◦ It focus on X-problems in designs, not to discuss for  Incorrect software reset sequences  Misinterpreted specifications

9. 9  Generating stimulus ◦ Using simulation waveforms as stimulus ◦ Using waveforms for X-analysis has the following advantages:  (1) It allows designers to partition a design into smaller blocks.  Easy to dump waveforms for any part of the design.  The formal analysis technique will be able to handle the blocks.  Parallel processing.  (2) It fits into verification flows whose testbenches cannot be symbolically simulated.  The testbenches are written in C++, SystemC and Verilog, and they cannot be symbolically simulated.  By dumping waveforms for X-analysis, our verification environment does not need to be changed.  The flow of X-analysis ◦ First, we partition the design and then perform logic simulation of the initialization sequence to dump a waveform for each design block.

10.  Constrained-Random Simulation ◦ Ideal : Automatically generates random and legal patterns  Advantage : Generate input scenarios that designers didn’t think of ◦ Practical : Writing constraints for DUV can be challenging  Under-constrained testbench  Produce illegal inputs, leading to the analysis of irrelevant states  Increasing verification quality  Over-constrained testbench  Can’t cover the whole valid input space and may miss bugs,  Reducing verification quality 10 Under-Constrainted example Over-Constrainted example

11. 11  Deciding what to check ◦ Face the designs contain a large number of registers  Designers need to specify which registers to check in order to avoid false alarms. ◦ One way is Using SystemVerilog’s $isunknown ◦ This approach may not be practical to specify everything that needs to be verified because the number of such registers may be large.  To address this problem ◦ Only check the registers that don’t have Xs in logic simulation.  It can identify potential problems that are masked due to X-optimism in logic simulation. The functions of right table can be used anywhere in SystemVerilog code.

12. 12  Enhancing Scalability ◦ First, execute symbolic simulation to a checkpoint. ◦ Then perform formal X-analysis. ◦ At the checkpoint  If any X is found, designers should check whether the X is acceptable or not  If the X is not acceptable, then a bug is found.  If the X is acceptable, then the non-X value in the design register should not cause any problem in the future.  So, it can simply execute logic simulation to the current checkpoint The process of X-analysis after temporal partitioning

13. 13  Overall Methodology ◦ (1) Partition the design so that each block can be verified efficiently by the formal X-analysis engine. ◦ (2) For a block, select checkpoints for temporal partitioning. Run logic simulation using the reset sequence to dump a waveform. X-free registers at those checkpoints are also identified. ◦ (3) Use waveform as stimulus to perform X-analysis on X-free registers for every interval according to the method. Potential Xs will be reported. ◦ (4) Repeat step 2 and 3 for all the blocks.

14. 14  I want to see ◦ The content of six-million gate design ◦ The effort of eXact  accuracy  scalability  Experiment setting ◦ Using a commercial symbolic simulator called Insight [12]. ◦ Running on a Linux server  Quad-Core Xeon processors (2.93 to 3.16 GHz)  Memory between 16G and 128G

15. 15  A six-million gate high-speed tester design ◦ Since the design was too large for formal X-analysis, partitioning was necessary.  To select appropriate block sizes for partitioning ◦ (1) Picked a block and ran symbolic simulation for a few cycles. ◦ (2) Measured the run time of symbolic simulation.  If the runtime seems to be reasonable, then the block is suitable for formal X- analysis. ◦ In this case, author found that 200K-300K is the maximum number of gates that symbolic simulation can handle efficiently.

16. 16  Chose checkpoint intervals according to simulation speed ◦ Goal to finish X-analysis of each block in at most two days with as few checkpoints as possible. ◦ There were several FIFOs inside the alp_cmem_eng block that were implemented using memory, so it need more time to simulation.  Provide the percentage of registers that need to be checked. ◦ Focusing only on the registers without X in logic simulation, it reduce the number of registers that need to be analyzed.

17. 17  Conclusions ◦ eXact methodology  To find X-problems, caused by uninitialized registers in RTL designs.  Easily to  Adopted into most simulation-based verification flows  Find potential X-problems  Thus it can significantly  Reducing design verification time  Improve design quality  My comments ◦ The methodology in this paper is useful to our design in gate- level simulation. ◦ We can faster to find X-problems than before.