1. 048918 VLSI Backend CAD Konstantin Moiseev – Intel Corp. & Technion Shmuel Wimer – Bar Ilan Univ. & Technion

2.  VLSI design flow overview  Introduction to algorithms and optimization  Backend CAD optimization problems: ◦ Design partitioning ◦ Technology mapping ◦ Floorplanning ◦ Placement ◦ Routing  Introduction to layout  Layout optimization and verification ◦ Layout analysis ◦ DRC and LVS checks ◦ Finding objects in the layout

3.  Dynamic programming ◦ Formal definition ◦ Simple examples  Slicing floorplans ◦ General description ◦ Dynamic programming algorithm  Technology mapping ◦ Problem definition ◦ Solution stages ◦ Dynamic programming algorithm

4.  Dynamic Programming decomposable  Dynamic Programming is a bottom-up technique that can be applied to solving optimization problems that are decomposable decomposable  A minimization problem is decomposable if each instance of the problem can be decomposed (perhaps in multiple ways) into “smaller” problem instances such that we can obtain a solution (not necessary an optimal one) of by combining optimal solutions of the decomposition sized-size  Each sub-problem has a positive decomposition size (d-size) that decreases in each decomposition step  Problem instances whose d-size is below some threshold are required to be directly solvable optimal substructure  In order to be solved by DP the problem has to exhibit optimal substructure

5.  Principle of optimality  Principle of optimality states that: 1.There is a monotonically increasing function such that:  Reminder:  is a cost of solution (not necessarily an optimal one)  is monotonically increasing if for, 2.There must be at least one way of breaking up into such that an optimal solution of results from combining arbitrary optimal solutions of the sub-problems and 3.We must be able to compute each such quickly by combining the optimal substructure  The problem decomposable in this way exhibits optimal substructure

6. sequential decision process  Solution by DP can be seen as a sequential decision process stage ◦ A stage is a set of all solutions to sub-problems with the same d-size: states ◦ Individual solutions in each stage are called states bottom-up ◦ The sequence of stages is built bottom-up, starting with stage containing solutions to atomic sub-problems and ending with stage containing solutions to the whole problem ◦ Only the states in stage are used to create states in stage pruned non-redundant ◦ Most of newly created states in stage are pruned, leaving only optimal (non-redundant) solutions memoization ◦ The optimal states are saved and re-used for next stage states generation – this is called memoization top-down backtracking ◦ After stage n is reached, optimal solution itself is reconstructed by top-down backtracking

7. 7 FloorplanGraph representation B2B2 B1B1 B3B3 B5B5 B4B4 B6B6 B 12 B9B9 B8B8 B7B7 B 10 B 11 B2B2 B1B1 B10B10 B5B5 B 12 B6B6 B3B3 B9B9 B8B8 B7B7 B 11 B4B4 Vertices - vertical lines. Arcs - rectangular areas where blocks are embedded. Floorplan is represented by a planar graph. A dual graph is implied.

8. 8  Actual layout is obtained by embedding real blocks into floorplan cells. ◦ Blocks’ adjacency relations are maintained ◦ Blocks are not perfectly matched, thus white area (waste) results  Layout width and height are obtained by assigning blocks’ dimensions to corresponding arcs. ◦ Width and height are derived from longest paths  Different block sizes yield different layout area, even if block sizes are area invariant.

9. 9 hh v v v v B2B2 B1B1 B3B3 B5B5 B4B4 B6B6 B 11 B3B3 B4B4 B5B5 B6B6 B8B8 B9B9 B 10 B1B1 B2B2 B7B7 h hh h B 12 B9B9 B8B8 B7B7 B 10 B 11 Slicing tree. Leaf blocks are associated with areas. v Top block’s area is divided by vertical and horizontal cut-lines

10. 10

12. By induction

14. 14 v1v1 v2v2 v3v3 v4v4 v1’v1’ v2’v2’ v3’v3’ += += + = uProof

15. 15 u pruned Size of new width-height list equals sum of lengths of children lists, rather than their product (redundant solutions are pruned). Proof

16. w h Pareto Pareto frontier (irredundant solutions) - saved Redundant solutions - pruned For continuous problems Pareto frontier is always convex

17. Proof

18. Proof

19. 19  A problem occurring in mapping logic circuit into new cell library  Given: ◦ Rooted binary tree T(V,E) called subject tree (cone of logic circuit), whose leaves are inputs, root is an output and internal nodes are logic gates with their I/O pins. ◦ A family of rooted pattern trees (logic cells of library), each associated with a non-negative cost (area, power, delay). Root is cell’s output and leaves are its inputs.  A cover of the subject tree is a partitioning where every part is matching an element of library and every edge of the subject tree is covered exactly once.  Find: ◦ A cover of subject tree whose total sum of costs is minimal.

20.  The problem: ◦ Find covering of subject graph (tree) with minimal area ? Pattern treesSubject tree

21. 21 r st u t 1 (2)t 2 (3)t 5 (5) t 4 (4) t 3 (3) t2t2 t1t1 t1t1 t3t3 3+2+2+3= 10 t4t4 t1t1 t3t3 4+2+3=9 t2t2 t5t5 3+5=8

22.  Brute force solution, recursive exploration: Start from root, try all possible patterns For each root pattern, try all possible patterns for its descendants, etc.  Run-time: ◦ For each node try all possible patterns ◦ For tree with nodes and patterns in library run time is ~ ◦ Should look for another approach

23.  Revealing optimal substructure: ◦ If pattern P is min cost match at some node of subject tree… ◦ then it must be that each leaf of pattern tree is also the root of some min cost matching pattern  Assume three different patterns match at root of subject tree ◦ Pattern P1 has 2 leaf nodes: a and b ◦ Pattern P2 has 3 leaf nodes: x, y and z ◦ Pattern P3 has 4 leaf nodes: j, k, l and m ◦ Which is the cheapest pattern if we know cost of each pattern? Based on R. Rutenbar slides

24.  Min cost tree cover ◦ Cheapest cover of root of subject tree is mincost(root) = min( patterncost(P1) + +, patterncost(P2) + + +, patterncost(P3) + + + + ) -Each rectangle means recursive call to mincost (subtree) - This shows optimal substructure of covering problem Based on R. Rutenbar slides mincost(a) mincost(b) mincost(x) mincost(y) mincost(z) mincost(j) mincost(k) mincost(l) mincost(m)

25.  Revealing overlapping sub-problems ◦ Assume we calculate tree cost top-down ◦ For picture below: node “y” in the subject tree  Will get its mincost cover computed (mincost(y)) when we put P2 at the root of the subject tree  … and again, when we put P3 at the root ◦ Instead, calculate tree cost bottom-up  Will have to calculate mincost(y) only once and store – memoization ◦ This reminds Fibonacci numbers example … Based on R. Rutenbar slides

26.  Assume table[node] = ∞ for all nodes at the beginning  The algorithm: Based on R. Rutenbar slides

27.  The algorithm works bottom up  For each node, checks all possible patterns that can be rooted at this node and combines each pattern’s cost with optimal solutions of sub-trees rooted at leafs of the pattern  Only optimal solution is saved in each node  Complexity: ◦ In each one of nodes patterns are checked:  The run-time complexity is  Space complexity is

28.  Cover following circuit using DP approach:

29. - NAND2 is only match for node a

30. - NAND2 is only match for node c - INV is only match for node b

31. - NAND2 is only match for node e - INV is only match for node d

32. -INV is possible match for node f - AOI21 is possible match for node f - NAND2 is only match for node g

33. -INV is only match for node h - NAND2 is possible match for node i - NAND3 is only match for node i

34. -NAND2 is only match for node j - NAND3 is possible match for node j

35.  Now backtrack to reveal optimal cover

38. 38 Legal shapes w h w h Block with minimum width and height restrictions ha*aw  Aha*aw  A

39. Shape functions 39 w h Hard library block w Discrete (h,w) values h

40. Corner points 40 5 2 2 5 25 2 5 w h

41. Algorithm This algorithm finds the minimum floorplan area for a given slicing floorplan in polynomial time. For non- slicing floorplans, the problem is NP-hard.  Construct the shape functions of all individual blocks  Bottom up: Determine the shape function of the top-level floorplan from the shape functions of the individual blocks  Top down: From the corner point that corresponds to the minimum top-level floorplan area, trace back to each block’s shape function to find that block’s dimensions and location. 41

42. 42 4 2 2 4 Block B: Block A: 5 5 3 3 Step 1: Construct the shape functions of the blocks

43. 43 4 2 2 4 Block B: Block A: 5 5 3 3 Step 1: Construct the shape functions of the blocks 2 4 h 6 w 26 4 5 3

44. 44 4 2 2 4 Block B: Block A: 5 5 3 3 Step 1: Construct the shape functions of the blocks 2 4 h w 26 4 6 3 5

45. 45 4 2 2 4 Block B: Block A: 5 5 3 3 w 26 2 4 h 4 6 hA(w)hA(w) Step 1: Construct the shape functions of the blocks

46. 46 4 2 2 4 Block B: Block A: 5 5 3 3 hB(w)hB(w) w 26 2 4 h 4 6 hA(w)hA(w) Step 1: Construct the shape functions of the blocks

47. 47 w 26 2 4 h 4 6 hB(w)hB(w) hA(w)hA(w) 8 w 26 2 4 h 4 6 hB(w)hB(w) hA(w)hA(w) hC(w)hC(w) 8 Step 2: Determine the shape function of the top-level floorplan (vertical)

48. 48 w 26 2 4 h 4 6 w 26 2 4 h 4 6 hB(w)hB(w) hA(w)hA(w) hB(w)hB(w) hA(w)hA(w) hC(w)hC(w) 3 x 9 4 x 7 5 x 5 88 Minimimum top-level floorplan with vertical composition Step 2: Determine the shape function of the top-level floorplan (vertical)

49. 49 2 x 43 x 5 5 x 5 Step 3: Find the individual blocks’ dimensions and locations w 26 2 4 h 4 6 (1) Minimum area floorplan: 5 x 5 (2) Derived block dimensions : 2 x 4 and 3 x 5 8 Horizontal composition