Presentation is loading. Please wait.

Presentation is loading. Please wait.

A Low-Power CAM Design for LZ Data Compression Kun-Jin Lin and Cheng-Wen Wu, IEEE Trans. On computers, Vol. 49, No. 10, Oct. 2000. Presenter: Ming-Hsien.

Published byRoland Ralph Houston Modified over 9 years ago

Similar presentations

Presentation on theme: "A Low-Power CAM Design for LZ Data Compression Kun-Jin Lin and Cheng-Wen Wu, IEEE Trans. On computers, Vol. 49, No. 10, Oct. 2000. Presenter: Ming-Hsien."— Presentation transcript:

1 A Low-Power CAM Design for LZ Data Compression Kun-Jin Lin and Cheng-Wen Wu, IEEE Trans. On computers, Vol. 49, No. 10, Oct. 2000. Presenter: Ming-Hsien Tsai

2 Outline 1. Introduction 2. CAM Structure 3. Removal of Redundant Comparisons ► Conditional Comparison Mechanism ► Redundancy Analysis 4. Conclusion

3 Outline 1. Introduction 2. CAM Structure 3. Removal of Redundant Comparisons ► Conditional Comparison Mechanism ► Redundancy Analysis 4. Conclusion

4 Introduction 1. CAM (Content Addressable Memory) has been considered the fastest architecture among all proposed hardware solutions for searching for a given string, as required in LZ77. 2. LZ77 is the lossless data compression algorithm

5 Outline 1. Introduction 2. CAM Structure 3. Removal of Redundant Comparisons ► Conditional Comparison Mechanism ► Redundancy Analysis 4. Conclusion

6 CAM Structure Traditional SRAM Cell Cross-coupled XOR GatePull-down Transistor Fig. 1. A typical CAM cell

7 CAM Structure Fig. 1. A typical CAM cell “1”“1” “0”“0” “1”“1” “1”“1”“0”“0” offon off High-impedance “0”“0”

8 CAM Structure Fig. 1. A typical CAM cell “0”“0” “1”“1” “1”“1” “1”“1”“0”“0” offon low “1”“1”

9 Outline 1. Introduction 2. CAM Structure 3. Removal Of Redundant Comparisons ► Conditional Comparison Mechanism ► Redundancy Analysis 4. Conclusion

10 Outline 1. Introduction 2. CAM Structure 3. Removal Of Redundant Comparisons ► Conditional Comparison Mechanism ► Redundancy Analysis 4. Conclusion

11 Conditional Comparison Mechanism Fig. 4. A typical match logic The masking of unnecessary comparison results on the match nodes Only match node is in the high-impedance when the word identical to input symbols

12 Conditional Comparison Mechanism Fig. 4. A typical match logic When all the words do not match “1”“1” “0”“0” “0”“0” “0”“0” “0”“0” If all words match “1”“1” “0”“0” “0”“0”

13 Conditional Comparison Mechanism Fig. 5. Conditional comparison mechanism Difference between CCM and typical match logic

14 Conditional Comparison Mechanism Fig. 5. Conditional comparison mechanism When all the words do not match “1”“1” “0”“0” “0”“0”“0”“0” “0”“0” If all words match “1”“1” “0”“0” “1”“1” “1”“1” “ OFF ” “0”“0” The static current is totally blocked when “ m i ” is low

15 Outline 1. Introduction 2. CAM Structure 3. Removal Of Redundant Comparisons ► Conditional Comparison Mechanism ► Redundancy Analysis 4. Conclusion

16 Redundancy Analysis ► Consider a typical data compressor using a CAM of 2,048 8-bit words as the buffer ► Assume that the input symbols are randomly distributed. On average, only 2048 x1/256 = 8 words can match any input symbol. 8 words can match any input symbol. ► There are 2048 – 8 = 2,040 words that will require the power.

17 Redundancy Analysis TABLE 1. Experimental Results on the Files from the Calgary Corpus

18 Outline 1. Introduction 2. CAM Structure 3. Removal Of Redundant Comparisons ► Conditional Comparison Mechanism ► Redundancy Analysis 4. Conclusion

19 Conclusion ► We showed that the redundant comparisons in the compression process can be removed by turning off the power supply to those words that do not need to participate, saving about 80 percent of the power consumption of the comparison mechanism as compared with the conventional CAM.

20 END

Download ppt "A Low-Power CAM Design for LZ Data Compression Kun-Jin Lin and Cheng-Wen Wu, IEEE Trans. On computers, Vol. 49, No. 10, Oct. 2000. Presenter: Ming-Hsien."

Similar presentations

Junzhou Huang, Shaoting Zhang, Dimitris Metaxas CBIM, Dept. Computer Science, Rutgers University Efficient MR Image Reconstruction for Compressed MR Imaging.

Junzhou Huang, Shaoting Zhang, Dimitris Metaxas CBIM, Dept. Computer Science, Rutgers University Efficient MR Image Reconstruction for Compressed MR Imaging.
1. 2 3 4 5 6 Figure. 01 7 8 9 10 11 (a) 8 * 8 array (b) 16 * 8 array.

Figure (a) 8 * 8 array (b) 16 * 8 array.
LEVERAGING ACCESS LOCALITY FOR THE EFFICIENT USE OF MULTIBIT ERROR-CORRECTING CODES IN L2 CACHE By Hongbin Sun, Nanning Zheng, and Tong Zhang Joseph Schneider.

LEVERAGING ACCESS LOCALITY FOR THE EFFICIENT USE OF MULTIBIT ERROR-CORRECTING CODES IN L2 CACHE By Hongbin Sun, Nanning Zheng, and Tong Zhang Joseph Schneider.
An On-Chip IP Address Lookup Algorithm Author: Xuehong Sun and Yiqiang Q. Zhao Publisher: IEEE TRANSACTIONS ON COMPUTERS, 2005 Presenter: Yu Hao, Tseng.

An On-Chip IP Address Lookup Algorithm Author: Xuehong Sun and Yiqiang Q. Zhao Publisher: IEEE TRANSACTIONS ON COMPUTERS, 2005 Presenter: Yu Hao, Tseng.
Chapter 12 Memory Organization

Chapter 12 Memory Organization
A Memory-Efficient Reconfigurable Aho-Corasick FSM Implementation for Intrusion Detection Systems Authors: Seongwook Youn and Dennis McLeod Presenter:

A Memory-Efficient Reconfigurable Aho-Corasick FSM Implementation for Intrusion Detection Systems Authors: Seongwook Youn and Dennis McLeod Presenter:
Pipelined Parallel AC-based Approach for Multi-String Matching Department of Computer Science and Information Engineering National Cheng Kung University,

Pipelined Parallel AC-based Approach for Multi-String Matching Department of Computer Science and Information Engineering National Cheng Kung University,
An Efficient IP Address Lookup Algorithm Using a Priority Trie Authors: Hyesook Lim and Ju Hyoung Mun Presenter: Yi-Sheng, Lin ( 林意勝 ) Date: Mar. 11, 2008.

An Efficient IP Address Lookup Algorithm Using a Priority Trie Authors: Hyesook Lim and Ju Hyoung Mun Presenter: Yi-Sheng, Lin ( 林意勝 ) Date: Mar. 11, 2008.
Bitmap Index Buddhika Madduma 22/03/2010 Web and Document Databases - ACS-7102.

Bitmap Index Buddhika Madduma 22/03/2010 Web and Document Databases - ACS-7102.
1 The Basic Memory Element - The Flip-Flop Up until know we have looked upon memory elements as black boxes. The basic memory element is called the flip-flop.

1 The Basic Memory Element - The Flip-Flop Up until know we have looked upon memory elements as black boxes. The basic memory element is called the flip-flop.
Power Efficient IP Lookup with Supernode Caching Lu Peng, Wencheng Lu*, and Lide Duan Dept. of Electrical & Computer Engineering Louisiana State University.

Power Efficient IP Lookup with Supernode Caching Lu Peng, Wencheng Lu*, and Lide Duan Dept. of Electrical & Computer Engineering Louisiana State University.
Introduction to CMOS VLSI Design CAMs, ROMs, and PLAs

Introduction to CMOS VLSI Design CAMs, ROMs, and PLAs
1 Single Reference Frame Multiple Current Macroblocks Scheme for Multiple Reference IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS FOR VIDEO TECHNOLOGY Tung-Chien.

1 Single Reference Frame Multiple Current Macroblocks Scheme for Multiple Reference IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS FOR VIDEO TECHNOLOGY Tung-Chien.
Die-Hard SRAM Design Using Per-Column Timing Tracking

Die-Hard SRAM Design Using Per-Column Timing Tracking
An Efficient and Scalable Pattern Matching Scheme for Network Security Applications Department of Computer Science and Information Engineering National.

An Efficient and Scalable Pattern Matching Scheme for Network Security Applications Department of Computer Science and Information Engineering National.
Pipelined Architecture For Multi-String Match Department of Computer Science and Information Engineering National Cheng Kung University, Taiwan R.O.C.

Pipelined Architecture For Multi-String Match Department of Computer Science and Information Engineering National Cheng Kung University, Taiwan R.O.C.
Chapter 1 Data Storage. 2 Chapter 1: Data Storage 1.1 Bits and Their Storage 1.2 Main Memory 1.3 Mass Storage 1.4 Representing Information as Bit Patterns.

Chapter 1 Data Storage. 2 Chapter 1: Data Storage 1.1 Bits and Their Storage 1.2 Main Memory 1.3 Mass Storage 1.4 Representing Information as Bit Patterns.
A Low-Power VLSI Architecture for Full-Search Block-Matching Motion Estimation Viet L. Do and Kenneth Y. Yun IEEE Transactions on Circuits and Systems.

A Low-Power VLSI Architecture for Full-Search Block-Matching Motion Estimation Viet L. Do and Kenneth Y. Yun IEEE Transactions on Circuits and Systems.
Adnan Ozsoy & Martin Swany DAMSL - Distributed and MetaSystems Lab Department of Computer Information and Science University of Delaware September 2011.

Adnan Ozsoy & Martin Swany DAMSL - Distributed and MetaSystems Lab Department of Computer Information and Science University of Delaware September 2011.
ECE 526 – Network Processing Systems Design Network Processor Architecture and Scalability Chapter 13,14: D. E. Comer.

ECE 526 – Network Processing Systems Design Network Processor Architecture and Scalability Chapter 13,14: D. E. Comer.

Similar presentations

Ads by Google