1. Lessons Learned The Hard Way: FPGA  PCB Integration Challenges Dave Brady & Bruce Riggins

2. Brady/Riggins Page 2 MAPLD 2005/P131 Agenda n Design Overview n Design Challenge Summary n Lessons Learned n Suggested Strategies

3. Brady/Riggins Page 3 MAPLD 2005/P131 System Design Challenges n Complex system implemented using multiple high-pin count FPGAs n PCB bus speeds > 150 Mhz n PCB physical size restricted n Implementation team (s) — System design, 2 engineers n System architecture, Embedded CPU h/w design — PCB design, 1 engineer n Functional design, PCB timing, PCB signal integrity — PCB physical design, 1 engineer n PCB place and route, design for manufacturing — FPGA design, 5 engineers n RTL HDL development — DSP design, 1 engineer n C algorithm development — Embedded software development, 2 engineers

4. Brady/Riggins Page 4 MAPLD 2005/P131 Conceptual Design Overview CPU & Embedded Platform Custom (ASIC) Logic Glue Logic PCB FPGA 1 FPGA Boot Module Communication Module Voltage Regulators/Generators DRAM Memory Modules Communication Module DSP Custom (ASIC) Logic Glue Logic FPGA 2 Clock Generators

5. Brady/Riggins Page 5 MAPLD 2005/P131 Design Challenge Summary 1. Overdriven signals 2. Cross talk 3. Simultaneous switching outputs 4. Meeting system performance specifications 5. Minimizing PCB manufacturing costs 6. Learning the FPGA device-specific I/O design rules 7. Maintaining (updating) FPGA symbols for the PCB schematic 8. Leveraging the complete design team

6. Brady/Riggins Page 6 MAPLD 2005/P131 Lessons Learned: Increasing PCB Costs Started with FPGA Timing PCB FPGA 1FPGA 2 Tp > Spec by 100 ps n FPGA 1 pin- to-pin timing exceeded spec by 100 ps n FPGA designer increased drive strength n Pin-to-pin timing meets spec

7. Brady/Riggins Page 7 MAPLD 2005/P131 Increasing PCB Costs Induced Signal Ringing on PCB (contd.) n Increasing drive strength on FPGA 1 output pin induced PCB signal ringing n PCB engineer identified PCB FPGA 1FPGA 2 Tp < Spec

8. Brady/Riggins Page 8 MAPLD 2005/P131 Increasing PCB Costs Induced Signal Ringing on PCB (contd.) n PCB engineer began inserting termination networks n Results: —  PCB component count —  PCB via count —  PCB trace count —  PCB routability —  PCB costs PCB FPGA 1FPGA 2 Tp < Spec R

9. Brady/Riggins Page 9 MAPLD 2005/P131 Lessons Learned: Increasing PCB Costs -- Scoping the Problem n Not an issue for a single trace n Design contained four 64-bit high- speed data busses — All 256 signals were impacted! PCB FPGA 1FPGA 2 Tp < Spec B1data(0:63) B2data(0:63) B3data(0:63) B4data(0:63)

10. Brady/Riggins Page 10 MAPLD 2005/P131 Lessons Learned: Big Busses  Cross Talk n Busses laid out on PCB with matching trace (tp) lengths n Identified by the PCB engineer n Traditional solutions: — Increase trace-to-trace separation — Leverage lower- dielectric PCB laminates PCB FPGA 1FPGA 2 Tp < Spec B1data(0) B1data(1) B1data(2) B1data(63)

11. Brady/Riggins Page 11 MAPLD 2005/P131 Lessons Learned: Big Busses  Simultaneous Switching Outputs n Grouping busses into the same pin bank improves PCB routability n FPGA pin banks are limited in the current they may source — Leads to SSO issues PCB FPGA 1FPGA 2 Tp < Spec B1data(0:63) B2data(0:63) B3data(0:63) B4data(0:63)

12. Brady/Riggins Page 12 MAPLD 2005/P131 Balance is the Key Signal Too SlowSignal Ringing FPGA I/O Drive Strength Setting Simultaneous Switching Output Issues Signal Cross Talk FPGA I/O Rail Voltage Setting

13. Brady/Riggins Page 13 MAPLD 2005/P131 TPD=Pass TPD=Fail Lessons Learned: Leveraging I/O Flexibility n Both FPGA devices designed to specs n Unable to meet system timing specs

14. Brady/Riggins Page 14 MAPLD 2005/P131 TPD=Pass TPD=Fail Leveraging I/O Flexibility (contd.) n Changed the physical location of signals on the FPGA n Unable to meet timing in one FPGA

15. Brady/Riggins Page 15 MAPLD 2005/P131 TPD=Pass Leveraging I/O Flexibility (contd.) n Changed the physical location of signals (again) n Finally met system timing specs n Simple for a single signal  Complex for wide busses

16. Brady/Riggins Page 16 MAPLD 2005/P131 Lessons Learned: The Domino Effect of Pin Swapping 1 2 3

17. Brady/Riggins Page 17 MAPLD 2005/P131 All Pins Are Not The Same CCLK DONE M0 M1 M2 Pin Bank 3GIO Clock PROG_B Single Ended Double Ended

18. Brady/Riggins Page 18 MAPLD 2005/P131 Virtex II Pro: Input AC Characteristics Source: Xilinx website

19. Brady/Riggins Page 19 MAPLD 2005/P131 Virtex II Pro: Input AC Characteristics Source: Xilinx website

20. Brady/Riggins Page 20 MAPLD 2005/P131 Virtex II Pro: Input AC Characteristics Source: Xilinx website

21. Brady/Riggins Page 21 MAPLD 2005/P131 Resolving Symbol Size 1500 Pin device 560 Pin device 100 Pin device

22. Brady/Riggins Page 22 MAPLD 2005/P131 Synchronizing the FPGA & PCB Flows Physical Placement & Connectivity

23. Brady/Riggins Page 23 MAPLD 2005/P131 Multiple Perspectives That Don’t Match FPGA and PCB design teams typically do not communicate

24. Brady/Riggins Page 24 MAPLD 2005/P131 Suggested Strategies: Eliminate Team Communication Barriers System Designer PCB Layout PCB Timing Analysis PCB Signal Integrity FPGA Designer Embedded System (CPU) Designer DSP Designer We do the FPGA I/O Design PCB (Schematic) Designer

25. Brady/Riggins Page 25 MAPLD 2005/P131 General Tips & Tricks n Leverage Signal Integrity “What if” Analysis Early — Anticipate signal ringing, cross talk, ground bounce, etc. — Develop system constraints to minimize PCB components — Make trade-offs at the system level n Run Signal Integrity Analysis on the PCB Design — Interactive part of the normal design process — NOT a design verification “check box” n Leverage Embedded Resistors — Some signal termination is un-avoidable — Minimize PCB size — Reduced PCB costs n Leveraging Gigabit Transceivers Reduces PCB Traces BUT — GHz signals  High-Speed (& cost) PCB laminates — Introduces additional PCB components (clock generators, voltage regulators, etc) — Introduces additional termination topology requirements n Re-partition the FPGA Design to Optimize PCB Performance — Alternative to leveraging Gigabit transceivers — Will not work for every design — Worked for this design

26. Brady/Riggins Page 26 MAPLD 2005/P131 Routing Comparison Routing after I/O Designer optimization — — 49% length reduction (320 ps less delay) — — Reduced routing congestion and excess

27. Brady/Riggins Page 27 MAPLD 2005/P131 PCB Layer Reduction PCB Optimized IO FPGA 1FPGA 2

28. Brady/Riggins Page 28 MAPLD 2005/P131 PCB design Pin-out assign Reduce Overall System Design Time n Concurrent design of FPGA and PCB n Optimize system performance & reduce manufacturing costs — Solution: Bi-directional FPGA I/O design FPGA design Pin-out changes PCB design I/O Designer Reduced Design Time Enhanced System Integration Optimized Performance Lowered Manufacturing Costs

29. Brady/Riggins Page 29 MAPLD 2005/P131 Provide PCB Designers an Intelligent FPGA I/O Design Tool

30. Brady/Riggins Page 30 MAPLD 2005/P131 Show FPGA Designers the PCB Design

31. Brady/Riggins Page 31 MAPLD 2005/P131 Provide Everyone Detailed Control

32. Brady/Riggins Page 32 MAPLD 2005/P131 Automate Pin Planning Routing after I/O Designer optimization — — 49% length reduction (320 ps less delay) — — Reduced routing congestion and excess

33. Brady/Riggins Page 33 MAPLD 2005/P131 100Mhz Clock Clock to Output = Pass Output to Setup = Pass Board Interconnect Budget = FAIL I/O Design Planning Benefits n Meet performance constraints — Overall timing constraints n FPGA in-chip n On board — PCB signal integrity constraints — Comply with FPGA technology I/O rules n Eliminate PCB signal layers PCB Optimized IO FPGA 1FPGA 2

34. Brady/Riggins Page 34 MAPLD 2005/P131 The Complete Flow Including PCB Physical Design n Flow Integration — Schematic to layout — Layout to I/O pin planning — FPGA Designer has visibility into the PCB design — PCB designer has access to I/O design rules — Fast pin swaps — Automatic bus untangling