1. CSET 4650 Field Programmable Logic Devices Dan Solarek Introduction to CPLDs Complex Programmable Logic Devices

2. 2 Logic Circuit Implementation We can implement a logic design with many different implementation technologies. Different implementation technologies offer a variety of design/performance tradeoffs. VHDL synthesis offers an easy way to target a model towards specific implementations. There are also retargetting tools which will convert a netlist from one technology to another (e.g., from a standard cell implementation to a Field Programmable Gate Array implementation).

3. 3 Logic Circuit Implementation Available implementation technologies include: Full Custom ICs Standard Cells Gate Arrays Field Programmable Gate Arrays (FPGAs) Complex PLDs (CPLDs) Simple Programmable Logic Devices (SPLDs) Standard SSI/MSI Logic

4. 4 Hierarchy of Logic Implementations Acronyms SPLD = Simple Prog. Logic Device PAL = Prog. Array of Logic CPLD = Complex PLD FPGA = Field Prog. Gate Array ASIC = Application Specific IC Common Resources Configurable Logic Blocks (CLB) Memory Look-Up Table (LUT) AND-OR planes Simple gates Input / Output Blocks (IOB) Bidirectional, latches, inverters, pullup/pulldowns Interconnect or Routing Local, internal feedback, and global Logic Standard Logic ASIC Programmable Logic Devices (FPLDs) Gate Arrays Cell-Based ICs Full Custom ICs CPLDs SPLDs (e.g., PALs) FPGAs today’s focus examine briefly

5. 5 Semicustom Devices Gate Arrays Gates already fabricated Interconnecting metalization used to customize design Cell-based ICs – Standard Cells Similar to PCB layout, but using predefined cells More efficient, but requires full mask set These mask-programmed devices are ‘customized’ by manufacturer

6. 6 Range of ASIC Design Styles Gates Routing Channel Gates Routing Channel Gates Standard ALU Standard Registers Gates Custom Control Logic Custom Register File Custom Design Standard Cell Gate Array Custom ALU Generally, these devices are not field programmable or reprogrammable.

7. 7 Gate Array A Gate Array consists of three parts: I/O pad area I/O buffer area internal cell area Customized by metalization to interconnect basic gates Vendor does this

8. 8 Gate Arrays Designer uses a library of standard cells. The design is mapped onto an array of transistors which is already created on a wafer; wafers with transistor arrays can be created ahead of time. A routing tool creates the masks for the routing layers and "customizes" the pre-created gate array for the user's design. Transistor density can be almost as good as standard cell. Design time advantages are the same as for standard cell. Performance can be very good; again, depends on quality of available library and routing tools.

9. 9 Gate Arrays Fabrication costs are lower than standard cells or full custom because the gate array wafers are mass produced. the non recurring engineering costs are lower because only a few (1- 3) unique routing masks have to be created for each design Fabrication time can be extremely short (1-2 weeks) because the wafers are already created and are only missing the routing layers. the more routing layers, the higher the cost, the longer the fabrication time, but the better usage of the available transistors on the gate array Almost all high volume production of complex digital designs are done using Standard Cells or Gate Arrays. gate arrays used to be more popular, but recently standard cells has shown a resurgence in use

10. 10 Standard Cells based on optimum-sized logic cells library elements are prepared by the ASIC vendor at transistor level (building block type) using various transistor sizes library elements are placed on the logic areas during physical implementation higher degree of integration than gate arrays faster than FPGAs

11. 11 Standard Cells One vendor’s list of standard cells

12. 12 Standard Cells Designer uses a library of standard cells an automatic place and route tool does the layout designer does not have to be a VLSI expert Transistor density and performance degradation depends on type of design being done. not bad for random logic can be significant for datapath type designs

13. 13 Standard Cells Quality of available libraries and design tools make a significant difference in results. Design time can be much faster than full custom because layout is automatically generated. Still involves creation of custom chip all masks must still be made manufacturing costs same as full custom. Fabrication time is the same as for full custom.

14. 14 Full Custom ICs Designer hand draws geometries which specify transistors and other devices for an integrated circuit. Designer must be an expert in VLSI (Very Large Scale Integration) design. Can achieve very high transistor density (transistors per square micron); unfortunately, design time can be very long (many months). Involves the creation of a a completely new chip, which consists of about a dozen masks (for the photolitographic manufacturing process). Mask creation is the expensive part. Offers the chance for optimum performance. Performance is based on available process technology, designer skill, and CAD tool assistance.

15. 15 Full Custom ICs Fabrication costs are high all custom masks must be made so non-recurring engineering costs (NRE) is high (in the thousands of dollars) if required number of chips is high then can spread these NRE costs across the chips. The first custom chip costs you about $200,000, but each additional one is much cheaper. Fabrication time from geometry submission to returned chips is at least 6-8 weeks. Full custom is currently the only option for mixed Analog/Digital chips.

16. 16 Three FPLD Types 1.Simple Programmable Logic Device (SPLD)  LSI device  Less than 1000 logic gates 2.Complex Programmable Logic Device (CPLD)  VLSI device  Higher logic capacity than SPLDs 3.Field Programmable Gate Array (FPGA)  VLSI device  Higher logic capacity than CPLDs

17. 17 SPLDs Simple PLDs Popular SPLD Architecture Types Programmable Logic Array, PLA Programmable Array Logic, PAL (Vantis) General Array Logic, GAL (Lattice) Architecture Differences AND versus OR implementation Programmability (e.g., EE) Fundamental logical block

18. 18 SPLDs Conventional programmable logic (PALs, PLAs, GALs) standard parts like GAL22V10 and PAL16R4 are available from multiple vendors Includes programmable logic cells to a limited degree (programming options in I/O cells, may have fixed AND/OR gates for logic), limited routing network. Lowest density of all programmable devices, however, can offer very high performance. SPLDs have nearly replaced TTL logic which used to be the normal approach to logic implementation

19. 19 CPLDs Complex PLDs Composition typically composed of 2-64 SPLDs interconnected using sophisticated logic includes macrocells – more about these later Economical for designing large systems Fast – switching speed

20. 20 CPLDs PALs and GALs are available only in small sizes equivalent to a few hundred logic gates For bigger logic circuits, complex PLDs or CPLDs can be used. CPLDs contain the equivalent of several PALs/GALs linked by programmable interconnections all in one integrated circuit (IC) CPLDs can replace thousands, or even hundreds of thousands, of individual logic gates increased integration density

21. 21 CPLDs Complex PLD's have arrays of PLD's on one chip, with an interconnection matrix connecting them. Timing peformance can be more predictable than FPGAs because of simpler interconnect structure. Density is normally less than most FPGAs (although high end CPLDs will have about the same densisty as low-end FPGAs). Performance of CPLDs is usually better than FPGAs, but depends on vendor, number of cells in CPLD, and compared FPGA.

22. 22 CPLDs The block diagram at left for the Cypress Semiconductor CPLD (37000 family) illustrates the general architecture of CPLDs

23. 23 CPLDs Complex Programmable Logic Devices Contain from 10-1000 macrocells Each macrocell is equivalent to around 20 gates Support up to 200 I/O pins The key resource in a CPLD is the programmable interconnect Tradeoff between space for macrocells and space for interconnect Careful design will limit the connections between macrocells

24. 24 FPGAs Field Programmable Gate Arrays The term FPGA is a generic term used to describe the highest density programmable logic devices currently available. Similar to microprocessors in complexity Slower than CPLDs – switching speeds Very low mass production cost

25. 25 FPGAs There are many different types from many different vendors. Composition: 64 to 10’s of thousands of logic blocks and flip-flops highest logic capacity of PLDs A single FPGA can replace tens of normal PLDs i.e., 22V10 type PLDs

26. 26 FPGAs The principle difference between PLDs and FPGAs are: Primitive FPGA 'logic cells' are more complex than PLD cells. Can program the routing between FPGA logic cells in addition to programming the logic cells themselves. Many FPGAs now offer embedded memory blocks in addition to logic blocks or other special features such as fast carry logic chains.

27. 27 FPGAs Design time advantages are the same as for standard cell. Performance is usually several factors to an order of magnitude lower than standard cell. Performance depends heavily on quality of FPGA technology. Densities are an order of magnitude lower than standard cell but an order of magnitude higher than normal PLDs. Very good for prototype design because many FPGAs are re-usable. Can be used to prototype and verify designs before investing in technologies with high start-up costs (e.g. full custom).

28. 28 FPGAs Can manufacture the first few boards of a new product using FPGAs and then replace with Gate Arrays when the production ramps up. FPGAs can be programmed on your desktop so fabrication time is not an issue. One of the attractions of FPGAs is the ability to prototype very quickly FPGAs offer the ability to fix bugs in a design without patching the Printed Circuit Board (PCB). Can be a career saver!

29. 29 Field-Programmable Gate Array (FPGA) A field-programmable gate array (FPGA) is an FPLD featuring a general structure that allows very high logic capacity. CPLDs feature logic resources with a wide number of inputs (AND planes) FPGAs offer narrower logic resources FPGAs offer a higher ratio of flip-flops to logic resources than do CPLDs.

30. 30 Xilinx XC9500 CPLD Series Devices designed for 2.5V, 3.3V, and 5V applications

31. 31 Programmability Options PLDs, CPLDs, and FPGAs have different types of programmability. initial programming and reprogramming One-time programmable: device is programmed once and holds its programming "forever" usually uses fuses to make/break links not reusable, but usually the cheapest discard device if changes are to be made

32. 32 Programmability Options UV-Erasable: programming is erasable with UV light needs a ceramic package with a window above the chip area package complexity adds expense to device usually remove socketed chip to erase/reprogram programming retained after power down non-volatile programming/erasing limited to 1000s of cycles

33. 33 Programmability Options Electrically Erasable: both erasing and reprogramming is accomplished with an electrical current device can be programmed/erased on circuit board, no special packaging or IC socket is needed erase time is much faster than UV erase programming retained after power down non-volatile programming/erasing limited to 1000s of cycles

34. 34 Electrically Erasable PLDs Conventional PLDs are either One-time programmable UV Erasable Must be placed in a programmer to program them EE PLDs can be programmed and erased in place A small (four wire) connection to a computer is needed Once programmed, will retain program indefinitely Never have to take the chip out of its circuit

35. 35 Programmability Options Static Random Access Memory (SRAM) Programming: configuration bits are stored in SRAM can be reprogrammed infinite number of times programming contents NOT retained after power down FPGA must be 'configured' every time on power up external non-volatile memory device required to hold device programming on power up contents of external device transferred to FPGA to configure the device. Altera, Xilinx corporations offer this type of FPGAs

36. 36 FPLD Programming Technologies User-programmable switches are the key to user customization of FPLDs. The first user-programmable switch developed was the fuse used in PLAs (only used in smaller devices). For CPLDs, the main switch technologies (in commercial products) are floating gate transistors like those used in EPROM (erasable programmable read-only memory) and EEPROM (electrically erasable PROM). For FPGAs, they are SRAM (static RAM) and antifuse.

37. 37 FPLD Capacities “ Equivalent gates ” refers loosely to the number of two- input NAND gates. The chart serves as a guide for selecting a device for an application according to the logic capacity needed. Each type of FPLD is inherently better suited for some applications than for others.

38. 38 Digital Technology Tradeoffs S

39. 39 Which Implementation Technology? Economic versus technical factors SPLD SSI/MSI semicustom technologies CPLD FPGA Gate Array Std. Cell Full Custom

40. 40 Evolution of Implementations 1960 1970 1980 1990 2000 SSI MSI LSI VLSI ‘standard components’ ‘semicustom components’ Gate Array Standard Cells Simple PLD CPLD FPGA parallel development

41. 41 Economic Factors Overhead... Cost Testing CostUnit Volume cost NRE costComponent    NRE = Non Recurring Engineering Essentially the cost to design the device

42. 42 SSI/MSISPLDFPGAGate array Standard cell Full custom Gates/ component 5 - 100 50 - 5K 100 - 10K 500 - 100K 10K - 500K 100K - 10M Cost/gateHigh Low NRE cost ($)-1-2K2-10K5-50K10-100K50K-5M Development time (weeks) -1-2 2-205-5020-200 Comparison of Implementation

43. 43 Comparison of Implementations Circuit cost as a function of volume Discrete Full custom Volume Cost

44. 44 Comparison of Implementations Density (gates per chip) Highest to lowest density: Full Custom, Standard Cell, Gate Array, FPGAs, CPLDs, SPLDs Performance Highest to lowest performance: Full Custom, Standard Cell, Gate Array, SPLDs, CPLDs, FPGAs. Performance of programmable technologies is in reverse order of their densities. Cost comparison Depends heavily on volume. If only a few hundred are needed, then FPGAs can be cheaper. If thousands are needed, then non- programmable technologies may be cheaper.

45. 45 Summary Full custom ICs can yield the best density and overall performance. Faster design time and ease of design are the main advantages of gate arrays and standard cells over full custom. Fast fabrication time and lower cost are the main advantages of gate arrays over standard cells. Gate arrays offer much higher density over FPGAs and are cheaper than FPGAs in volume production.

46. 46 Summary FPGAs primary advantage over gate arrays is 'instant' fabrication time (programmed on desktop). FPGAs are also cheaper than gate arrays in low volume. Densities are reaching 100's of thousands of gates/chip. Can be used to prototype full custom/standard cell designs. SPLDs still hold a speed advantage over most FPGAs and are useful for high speed decoding and speed critical interface logic.

47. 47 Summary Most prototypes and many production designs now use FPLDs The most compelling advantages of FPLDs are low startup cost low financial risk quick manufacturing turnaround easy design changes The last two advantages are because the end user programs the device