1. CMOS DIFFERENTIAL AMPLIFIER

2. INTRODUCTION Bias and gain sensitive to device parameters (µC ox,V T ); sensitivity can be mitigated but often paying price in performance or cost (gain, power, device area, etc.) Vulnerable to ground and power-supply noise (in dense IC’s there is cross-talk, 60 Hz coupling, substrate noise, etc.) Many signal sources exhibit ”common-mode” drift that gets amplified. Three problems in single-transistor amplifier stages:

3. SOLUTION Represent signal by difference between two voltages: Differential amplifier:  amplifies difference between two voltages  rejects components common to both voltages

4. DIFFERENTIAL AMPLIFIER definitions Common mode rejection ratio (CMRR)  CMRR is a measure of how well the differential amplifier rejects the common-mode input voltage in favor of the differential-input voltage. Input common-mode range (ICMR)  The input common-mode range is the range of common-mode voltages over which the differential amplifier continues to sense and amplify the difference signal with the same gain.  Typically, the ICMR is defined by the common-mode voltage range over which all MOSFETs remain in the saturation region. Output offset voltage (V OS (out))  The output offset voltage is the voltage which appears at the output of the differential amplifier when the input terminals are connected together. Input offset voltage (V OS (in) = VOS)  The input offset voltage is equal to the output offset voltage divided by the differential voltage gain.

5. Why Differential? One of the most widely used analog block  High-performance mixed-signal circuits Outline:  Review of single-ended and differential operation  Description of basic differential pair Large signal and small signal analyses  Common Mode Rejection Ratio (CMRR) Concept, formulation  Diff pair with diode-connected and current-source loads  Gilbert cell

6. Single-ended  Signal measured with respect to a fixed potential (e.g. gnd) Differential  Signal measured btwn 2 nodes with equal and opposite signal excursions around a fixed potential (see figure above)  Dotted line -> common-mode level Single-Ended and Differential Operation

7. SE & Diff - discussed Diff circuit more immune to noise e.g. Power Supply Noise  Single-Ended: Supply varies by  V  Vout changes by approx. same amount  Differential (symmetric circuit) Noise on supply affects V X and V Y, not V X -V Y (V out ) High-Noise Immunity – rejects common signal (noise)

8. Advantages of Differential Circuit 2 adjacent lines  one carries small, sensitive signal  one carries large clock waveform  Capacitive coupling btwn L1 and L2 Transitions on L2 corrupt signal on L1 Sensitive signal distributed as 2 equal magnitude and opposite phases Clock placed midway, btwn the 2 Clock transition disturbs differential phases by equal amounts -> difference intacts Diff output not corrupted -> rejects common-mode noise

9. Another advantage of diff amp. In a single CS amplifier, the maximum swing is V DD -(V GS -V TH ) In a differential pair it can be shown that the swing of V X -V Y can reach 2[V DD -(V GS -V TH )].

10. Basic Differential Pair Amplify diff signal. Mechanism?  Concept: incorporate two identical SE signal paths to process the two phases  The resulting circuit offers advantages of diff signaling: e.g. High rejection of supply noise, high output swings, etc.  What if input CM level changes? Bias currents of M1 and M2 changes -> vary gm of devices (hence the gain) -> vary output CM level (lowers maximum allowable output swings)  Example: If input CM is excessively low (b): Min values of V in1 and V in2 may turn off M1 and M2 Lead to severe clipping at output  How to solve the problem?

11. Diff Pair (cont.) Add current source I SS  Makes I D1 + I D2 independent of V in,CM  I D1 =I D2 =I SS /2 when V in1 =V in2, output CM level = V DD -R D I SS /2 Main function:  suppress effect of input CM level variations on operation of M1 and M2, and output level

12. Assume -  V in1 –V in2 <  Case 1: V in1 more –ve than V in2  M1 off, M2 on -> I D2 =I SS V out1 = V DD V out2 = V DD – I SS R D2 Case 2: As V in1 brought closer to V in2  M1 gradually turns on Draws a fraction of I SS from R D1 (I SS =I D1 +I D2 ), lowering V out1 Eventually, V in1 more +ve than V in2  I SS flows through M1 (on), none through M2 (off)  V out2 = V DD  V out1 = V DD -I SS R D1 See diagram above for the complete transition Diff Pair – Qualitative Analysis

13. Cont’d … 2 important characteristics revealed from prev analysis  Char 1: output’s maximum and minimum levels well-defined (V DD and V DD -R D I SS ), independent of input CM level  Char 2: small-signal gain (slope of V out1 -V out2 vs. V in1 -V in2 ) is maximum for V in1 =V in2 Gradually falling to zero as |V in1 -V in2 | increases i.e. circuit becomes more nonlinear as input voltage swing increases Circuit is in equilibrium when V in1 =V in2

14. SMALL-SIGNAL DIFFERENTIAL VOLTAGE GAIN For |ΔV in |≈0 (sufficiently small) we have: where g m is that of a NMOS with a current of I SS /2

15. Single-ended Differential Voltage Gain

16. Example Let V DD =3V, (W/L) 1 =(W/L) 2 =25/0.5 µ n C OX =50µA/V 2, V TH =0.6V, λ=0, γ=0, R SS =500Ω What is the required input CM for which R SS sustains 0.5 V? Calculate RD for a differential gain of 5 What happens at the output if the input CM level is 50 mV higher than the value calculated in (a)?

17. NMOS Differential Amplifiers Small Signal Analysis   

18. Common-Mode Gains We have seen two types of common- mode gain: A V,CM : Single-ended output due to CM signal. A V,CM-DM : Differential output due to CM signal.

19. Common-Mode Rejection Ratio (CMRR) Definitions In both cases we want CMRR to be as large as possible, and it translates into small matching errors and R SS as large as possible

20. MOS Loads (a) Diode-connected load (b) Current-Source load

21. MOS Loads: Analysis Method Differential Analysis: Use half-circuit method, with source node at virtual ground. Common-Mode Analysis: Again use half-circuit method, with appropriate accommodation for parallel transistors, and for R SS.

22. MOS Loads: Differential Gain Formulas

23. Problems with Diode-connected MOS Loads Tradeoff among swing, gain and CM input range: In order to achieve high gain, (W/L) P must be sufficiently low. Therefore PMOS overdrive voltage must be sufficiently low. As a result CM signal range is reduced.

24. Overcoming Diode-connected Load swing problem for higher gains: Use PMOS current sources which reduce g m of diode-connected MOS, instead of lowering (W/L) P of load. Gain can be increased by factor of 5.

25. Problems with Current-Source MOS Loads In sub-micron technologies, it’s hard to obtain differential gains higher than 10- 20.

26. Solution to low-gain problem: Cascoding

27. Gilbert Cell Combine 2 properties of diff pair to develop a versatile building block  Small-signal gain of diff pair = f(tail current)  2 transistors in a diff pair provides a means of steering tail current to one of two destinations Variable Gain Amplifier (a)  Used in a system where signal amplitude may experience large variations and requires inverse changes in gain  V cont defines tail current hence the gain Max gain = f(voltage headroom limitations, device dimensions)

28. Cont’d… 2 diff pairs that continuously vary gain from a –ve to +ve value  Amplify inputs by opposite gains A 1 =-g m R D, A 2 =g m R D, A 1 =f(V cont1 ), A 2 =f(V cont2 ) A 1 and A 2 follows the changes in I 1 and I 2  How to combine the outputs into a single final output?

29. Cont’d… Sum the 2 outputs  Produce V out = V out1 + V out2 = A 1 V in + A 2 V in How to realize with transistors?  Note: V out1 =R D I D1 -R D I D2 V out2 =R D I D4 -R D I D3    V out1 +V out2 =R D (I D1 +I D4 )-R D (I D2 +I D3 ) We don’t add voltages, but add currents by shorting the corresponding drain terminals -> I sum generate output voltage e.g. I 1 =0, V out =g m R D V in ; I 2 =0 -> V out =-g m R D V in ; I 1 =I 2 -> gain=0  To change amplifier gain monotonically, I 1 and I 2 must vary in opposite directions HOW to change amplifier gain/vary the currents in opposite directions?

30. Cont’d… Recall diff pair… yes, a diff pair  Observation: For large |V cont11 -V cont2 | all of tail current steered to one of top diff pair Gain -> most positive or most negative value Redraw the circuit -> GILBERT CELL Note: V in and V cont are interchangeable and still works as a VGA