1. 10/11/2015 Operational Amplifier Characterization Chapter 3

2. Contents  Input offset voltage  Input bias and input offset currents  Output impedance  Differential and common-mode input impedances  DC gain, bandwidth, gain-bandwidth product  Common mode and power supply rejection ratios  Higher frequency poles, settling time  Slew rate  Noise in operational amplifier circuits

3. The Ideal Op-amp  Input resistance, R in    Output resistance, R o = 0  Open loop voltage gain, G    Bandwidth B    V o = 0 when V + = V - (i.e., the common – mode gain is zero and the CMRR approaches infinity)

4. The Typical Op-amp  Input resistance, R in  2 M , not   Output resistance, R o = 75 , not 0  Open loop voltage gain, G  1x10 5, not   Bandwidth B  1 MHz, not   Offset current, I io = 20 nA  Offset voltage, V io = 2 mV  Slew rate, SR = 0.7 V/ms

5. Input offset voltage  When voltage at both inputs is zero, the output should be zero  Op amps do not have perfectly balanced input stages owing to manufacturing variations  The difference in input voltages necessary to bring the output to zero is called the input offset voltage.  Usually op-amps make provision for trimming the input offset voltage to zero

6. Effect  V i0 and the large value of the open-loop gain of the op- amp act to drive V 0 to negative saturation.  The magnitude and polarity of V i0 varies from op amp to op amp. So for some op amp, the output will be driven to +V sat and others will be driven to -V sat.

7. Measurement  Since E i = 0V, V 0 should equal 0V. The error in V 0 due to V i0 is given by V 0 = error voltage due to V i0 = V i0 (1 + R f /R i )  The output error voltage results whether the circuit is used as an inverting or as a noninverting amplifier.  A bias-current compensating resistor (a resistor in series with the (+) input) has no effect on this type of error in the output voltage due to V i0.

8. Practical side of input offset voltage  For 411 and 741, we use a pot. between pins 1 and 5, with the wiper connected to -Vcc as offset null  typical offset voltages: 411 => 0.8 mV 741 => 2 mV

9. Input bias current  Although ideal op-amp inputs draw no current, some bias current must enter each input terminal in the actual case.  I bias is the base current of the input transistor, and a typical value is 2  A.  When the source impedance is low, I bias has little effect, since it causes a relatively small change in input voltage. However, in high-impedance circuits, a small current can lead to a large voltage.

10. Modeling  The bias current can be modeled as two current sinks. The values of these sinks are independent of the source impedance.  The bias current is defined as the average value of the two current sinks. Thus I bias = (I B+ + I B- )/2  The difference between the two sink values is known as the input offset current, I io and is given by I io = I B+ - I B-.

11. Effect of (-) input bias current  Output voltage should be zero ideally: The fact that a voltage component will be measured is due strictly to I B-  For simplicity, assume that the input offset voltage is 0V  The bias current is furnished from the output terminal. Since negative feedback forces the differential input voltage to 0V, V 0 must rise to supply the voltage drop across R f. Thus, the output voltage error due to I B- is found from V 0 = R f I B-.  I B+ flows through 0 , so it causes no voltage error.

12. Effect of (+) input bias current  V 0 should ideally equal 0V. However, the positive input bias current I B+ flows through the internal resistance of the signal generator.  I B+ sets up a voltage drop of R G­ I B+ across resistor R G and applies it to the (+) input.  The differential input voltage of 0V, so the (-) input is also at R G I B+  Since there is 0 resistance in the feedback loop, V 0 equals R G I B+.

13. Reducing the effect of input bias current  It is possible to reduce the output dc voltage caused by the input bias current by connecting the op-amp as shown in fig  This method consists of introducing a resistance R 3 in series with the noninverting input lead  From a signal point of view, R 3 has a negligible effect. The appropriate value for R 3 can be determined by analyzing the circuit  I B+ = I B- = ­I B, results in R 3 = R 2 /(1 + R 2 /R 1 ) = R 1 R 2 /(R 1 + R 2 )

14. Output Impedance  Typical values for the open-loop output resistance R 0 are 75 to 100   We wish to find the output resistance of a closed-loop amplifier  To do this, we short the signal source, which makes the inverting and non-inverting configurations identical and apply a test voltage V x to the output  Then the output resistance R out  V x /I can be obtained by straightforward analysis of the circuit

15.  V = -V x R 1 /(R 1 + R 2 ) = -  V x  I = V x /(R 1 + R 2 ) + (V x - AV)/R 0  = V x /(R 1 + R 2 ) + (1 + A  )V x /R 0  Thus 1/R out = I/V x = 1/(R 1 + R 2 ) + (1 + A  )/R 0  where the constant  is defined as   = R 1 /(R 1 + R 2 )

16.  This means that the closed-loop output resistance is composed of two parallel components, R out = [R 1 + R 2 ] || [R 0 /(1 + A  )]  Normally R 0 is much smaller than R 1 + R 2, resulting in R out  R 0 /(1 + A  )  The closed-loop output resistance is smaller than the op amp open-loop output resistance by a factor equal to the amount of feedback, 1 + A .  R out  R 0 /A  for A  >>1

17. Differential and Common mode input impedance  As shown in fig, the op amp has a differential input resistance R id seen between the two input terminals.  In addition, if the two input terminals are tied together and the input resistance (to ground) is measured, the result is the common-mode input resistance R icm.  Typical values for the input resistances of general- purpose op amps using bipolar junction transistors are R id = 1 M  and R icm = 100 M .

18. DC gain, bandwidth, gain-bandwidth product  The differential open-loop gain of op amp is not infinite; rather, it is finite and decreases with frequency.  Fig shows a plot for |A|, with the numbers typical of most general-purpose op amps (such as 741).  Although the gain is quite high at dc and low frequencies, it starts to fall off at a rather low frequency (10 Hz in this example).  The uniform -20 dB/decade gain rolloff shown is typical of internally compensated op amps.

19. Common mode and power supply rejection ratios  The power supply rejection ratio (PSRR) is a measure of the ability of the op-amp to ignore changes in the power supply voltage.  The PSRR is the ratio of the change in V o to the total change in power supply voltage.  For example, if the positive and negative supplies vary from  5 V to  5.5 V, the total change is 11 – 10 =1 V. PSRR is usually specified in microvolts per volt or sometimes in decibels. Typical op-amps have a PSRR of about 30  V / V

20. Frequency Compensation  Many op amps are internally compensated.  Internal frequency compensation capacitor prevents the op amp from oscillating by decreasing the op amp's gain as frequency increases. Otherwise there would be sufficient gain and phase shift at some high frequency where enough output signal could be fed back to the input and cause oscillations.  The trade-off for frequency stability are limited small- signal bandwidth, slow slew rate, and reduced power bandwidth.

21. Slew Rate  Slew rate is a measure of the speed at which the output signal can change.  Slew rate is related to the power bandwidth, f p, which is defined as the frequency at which a sine wave output, at rated output voltage, starts to experience distortion.  If the output signal is V 0 = V sin 2  f p t, Then the maximum slope is SR = dV / dt | max = 2  f p V  The power bandwidth is given by f p = SR / 2  V

22. Noise in op-amp circuits  Electronic circuits are susceptible to noise and op-amp is not an exception. Apart from external noise, op-amp has internal noise sources like bias current, drift and internal components.  Noise is also amplified by op-amp, just as offset voltage and signal voltage.  Even if there were no external noise, there would still be noise in the output voltage caused by the op amp. This internal op amp noise is modeled most simply by a noise voltage source E n.

23.  The 741 op amp has 2  V of total noise over a frequency of 10 Hz to 10 kHz.  This noise voltage is valid for source resistors (R i ) between 100  and 20 k .  The noise voltage goes up directly with R i once R i exceeds 20 k . Thus R i should be kept below 20 k  to minimize noise in the output.

24. Measures to minimize internal noise  Keep series input resistors and the feedback resistors as low in value as practically possible to satisfy circuit requirements  Bypass feedback resistor with a small capacitor (  3 pF) which will reduce noise gain at higher frequencies  Never connect a capacitor across the input resistor or from (-) input to ground. There will always be a few pF of stray capacitance from (-) input to ground due to wiring