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R. Kass US LC Conference 1 Design and Fabrication of a Radiation-Hard 500-MHz Digitizer Using Deep Submicron Technology R. Kass The Ohio State University.

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Presentation on theme: "R. Kass US LC Conference 1 Design and Fabrication of a Radiation-Hard 500-MHz Digitizer Using Deep Submicron Technology R. Kass The Ohio State University."— Presentation transcript:

1 R. Kass US LC Conference 1 Design and Fabrication of a Radiation-Hard 500-MHz Digitizer Using Deep Submicron Technology R. Kass The Ohio State University July 29, 2004 S. Smith SLAC K.K. Gan, M.O. Johnson, R.D. Kass, A. Rahimi, C. Rush The Ohio State University

2 R. Kass US LC Conference 2 Presentation Outline l NLC Requirements l ADC (“digitizer”) Design l Progress Report l Plans

3 R. Kass US LC Conference 3 l NLC will collide 180-bunch trains of e - and e + : n bunch spacing: 1.4 ns n alignment of individual bunches in a train: < 1  m n BPM determines bunch-to-bunch misalignment  high bandwidth kickers bring the train into better alignment on next machine cycle  multi-bunch BPM system with digitizers: 11-bit effective resolution 500 MHz bandwidth 2 G samples/s Beam Position Monitor Requirements at NLC

4 R. Kass US LC Conference 4 Requirements of NLC Digitizers FunctionQty.Resolution (eff. bits) Bandwidth (MHz) Comments LLRF Control13,00011100Slightly beyond state-of-the-art Structure BPM22,00085Existing technology “Quad” BPM10,0001112Existing technology Multi-bunch BPM1,20011500Well beyond state-of-the-art Total46,200 important to demonstrate feasibility of high speed/resolution digitizers  redesign of low level RF technology is needed without the digitizers

5 R. Kass US LC Conference 5 Proposal l Design a digitizer chip using deep-submicron technology (0.25  m) n use enclosed layout transistors and guard rings ☺radiation hard: > 60 Mrad ☺no need for costly shielding and long cables ☺easy access to electronics for testing and maintenance l Extensive experience in chip design using Cadence n designed radiation-hard chips for CLEO III, ATLAS, CMS l Why OSU is interested? n help to solve a challenging NLC problem n potential applications in HEP l Holtkamp Committee rankings: 2 on scale of 1 to 4 (lowest)  funded for 2003-4 and 2004-5

6 R. Kass US LC Conference 6 12-bit Pipelined Digitizer l input crudely digitized by 1st 3-bit cell  digitized value subtracted from input  difference is amplified by 8 and sent to 2nd 3-bit cell… 13 bit: round to 0 or 12 bit

7 R. Kass US LC Conference 7 l most challenging digitizer: 11 bit, 2 G samples/s, 500 MHz bandwidth l input: sequence of doublets at 1.4 ns batch spacing n characterize with one parameter: pulse height n minimum sampling: 1/1.4 ns = 714 MHz  interleaving 3 digitizers for redundancy  2 G samples/s Digitizer for Multi-bunch BPM

8 R. Kass US LC Conference 8 l submicron CMOS supply voltage: 2.5 V  differential signal: ~ 1.6 V full swing  LSB: 1.6 V/2 12 = 390  V  stability/accuracy of comparator thresholds, amplifier & S/H gains, charge injection: 195  V = 0.5 LSB = 0.5/2 12 → 0.012% Precision

9 R. Kass US LC Conference 9 l gain-bandwidth requirement: n assume 0.7 ns for sample and 0.7 ns for hold n settling to 0.5 LSB for 12-bit digitizer requires 9  : 0.5/2 12 ~ e -9   ns/9  78 ps  rise time  2.2  ps  gain x bandwidth  8 x 1/2  GHz  IBM process SiGe BiCMOS 6HP/6DM via MOSIS: ☺40 GHz NPN bipolar transistors Fabrication Process

10 R. Kass US LC Conference 10 3-Bit Cell

11 R. Kass US LC Conference 11 l Simulate with Cadence sample/hold + flash ADC/flip-flop: designed/simulated from schematic with parasitic capacitances multiplexer: logic is fast but somewhat noisy op-amp + encoder: use real devices in simulation 3-Bit Cell Status

12 R. Kass US LC Conference 12 l design and simulated from schematic with parasitic capacitances switch-on resistance small enough to allow 9  in 700 ps switching offset (noise) largely cancelled with dummy switch: n 100 mV  1 mV Sample/Hold Status

13 R. Kass US LC Conference 13 Cadence Simulation of Sample/Hold Progress switch charge injection Amplifier: ideal Amplifier: Jan. 04 design Amplifier: July 04 design

14 R. Kass US LC Conference 14 AMP Specs rise time goal: 171 ps  achieve:186 ps need  V=195  V for 12-bit precision Simulation of Amplifier January 2004  V=298  V July 2004  V=194  V

15 R. Kass US LC Conference 15 Offsets differ by ~2.8mV Issues to be resolved: Offset from S/H not constant. Offset is a function of input signal slope. Current S/H Simulation Issue VT(“/vin”) ≡ input to 1st S/H VT(“/out2”) ≡ Output from 2nd S/H

16 R. Kass US LC Conference 16 l Year 2004-5: n complete design of amplifier + 3-bit cell n layout, submission, and testing of the building block circuits l Year 2005-7 n layout, submission, and testing of the prototype digitizer n radiation hardness tests n continued system design of prototype 11-bit digitizer Plans

17 R. Kass US LC Conference 17 EXTRA SLIDES FOLLOWS

18 R. Kass US LC Conference 18


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