1. Electronic System Design GroupInstrumentation DepartmentRob Halsall et al.Rutherford Appleton Laboratory17 October 2001 Clock Distribution Scheme LVDS CLOCK DC CNTRL DATA VME FPGA TTCrx ASIC Back End FPGA XTAL Front End Module 1 Front End Module 8 LVDS CLOCK backup x8 x4 DCM XC2V40 XC2VXXXX Rear I/O Clock

2. Electronic System Design GroupInstrumentation DepartmentRob Halsall et al.Rutherford Appleton Laboratory17 October 2001 Boundary Scan Distribution Chain Scheme Boundary Scan Switch CPLD Jumpers On Board Con 1 On Board Con 2 On Board Con 3 On Board Con 4 Back plane Front Panel VME Interface FE Modules Back End FPGA Clock FPGA VME FPGA CPLD FLASH Jumpers On Board Con 1 On Board Con 2 On Board Con 3 On Board Con 4 Back plane Front Panel VME Interface FE Modules Back End FPGA Clock FPGA VME FPGA CPLD FLASH VME FPGA

3. Electronic System Design GroupInstrumentation DepartmentRob Halsall et al.Rutherford Appleton Laboratory17 October 2001 FPGA Configuration Scheme(s) VME FPGAs Back End FPGAs XC2VXXXX Front End FPGAs XC2VXXXX FLASH Memory Clock & Delay FPGAs XC2VXXXX Always Boots on Power up FLASH Memory(s) Reconfigure Flash via download cable only Optionally Boot on Power up, optionally trigger configuration via software Reconfigure Flash via download cable, optionally reconfigure FLASH via Software Optionally re-configure FPGAs via Software direct