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CWRU EECS 317 EECS 317 CAD Computer Aided Design LECTURE 3: Synopsys Simulator Instructor: Francis G. Wolff Case Western Reserve University.

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Presentation on theme: "CWRU EECS 317 EECS 317 CAD Computer Aided Design LECTURE 3: Synopsys Simulator Instructor: Francis G. Wolff Case Western Reserve University."— Presentation transcript:

1 CWRU EECS 317 EECS 317 CAD Computer Aided Design LECTURE 3: Synopsys Simulator Instructor: Francis G. Wolff wolff@eecs.cwru.edu Case Western Reserve University This presentation uses animation: please viewshow

2 CWRU EECS 317 Review: Tri-State buffer oe y x ENTITY TriStateBuffer IS PORT(x:INstd_logic; y:OUTstd_logic; oe: INstd_logic ); END; ARCHITECTURE Buffer3 OF TriStateBuffer IS BEGIN WITH oe SELECT y <= x WHEN ‘1’, -- Enabled: y <= x; ‘Z’ WHEN OTHERS; -- Disabled: output a tri-state END;

3 CWRU EECS 317 Review: ROM: 4 bit Read Only Memory Y1Y1 Y0Y0 Y2Y2 Y3Y3 A0A0 A1A1 D0D0 OEOE 4 by 1 bit ROM ARRAY

4 CWRU EECS 317 Review: ROM: 4 bit Read Only Memory ENTITY rom_4x1 IS PORT(A:IN std_logic_vector(1 downto 0); OE:IN std_logic; -- Tri-State Output D:OUT std_logic ); END; ARCHITECTURE rom_4x1_arch OF rom_4x1 IS SIGNAL ROMout: std_logic; BEGIN BufferOut: TriStateBuffer PORT MAP(ROMout, D, OE); WITH A SELECT ROMout <= ‘1’ WHEN “00”, ‘0’ WHEN “01”, ‘0’ WHEN “10”, ‘1’ WHEN “11”; Component declaration name Component Instance

5 CWRU EECS 317 Component Declaration/Instance relationship ARCHITECTURE rom_4x1_arch OF rom_4x1 IS COMPONENT TriStateBuffer PORT (x: IN std_logic; y: OUT std_logic, oe: IN std_logic); END COMPONENT; SIGNAL ROMout: std_logic; BEGIN BufferOut: TriStateBuffer PORT MAP(ROMout, D, OE); WITH A SELECT ROMout <= ‘1’ WHEN “00”, ‘0’ WHEN “01”, ‘0’ WHEN “10”, ‘1’ WHEN “11”; END; ARCHITECTURE rom_4x1_arch OF rom_4x1 IS COMPONENT TriStateBuffer PORT (x: IN std_logic; y: OUT std_logic, oe: IN std_logic); END COMPONENT; SIGNAL ROMout: std_logic; BEGIN BufferOut: TriStateBuffer PORT MAP(ROMout, D, OE); WITH A SELECT ROMout <= ‘1’ WHEN “00”, ‘0’ WHEN “01”, ‘0’ WHEN “10”, ‘1’ WHEN “11”; END; Colon (:) says make a Component Instance Component Declaration Component Instance Name: BufferOut

6 CWRU EECS 317 Component Port relationship BufferOut: TriStateBuffer PORT MAP(ROMout, D, OE); oe y x COMPONENT TriStateBuffer PORT (x: IN std_logic; y: OUT std_logic, oe: IN std_logic); END COMPONENT; COMPONENT TriStateBuffer PORT (x: IN std_logic; y: OUT std_logic, oe: IN std_logic); END COMPONENT; ENTITY rom_4x1 IS PORT(A:IN std_logic_vector(1 downto 0); OE:IN std_logic; -- Tri-State Output D:OUT std_logic ); END; OE  IN  oe  IN D  OUT  y  OUT

7 CWRU EECS 317 Full Adder: Architecture ARCHITECTURE adder_full_arch OF adder_full IS BEGIN Sum<= ( x XOR y ) XOR Cin; Cout<= ( x AND y ) OR (Cin AND (x XOR y)); END; ARCHITECTURE adder_full_arch OF adder_full IS BEGIN Sum<= ( x XOR y ) XOR Cin; Cout<= ( x AND y ) OR (Cin AND (x XOR y)); END;

8 CWRU EECS 317 adder_full.vhd: complete file ARCHITECTURE adder_full_arch OF adder_full IS BEGIN Sum<= ( x XOR y ) XOR Cin; Cout<= ( x AND y ) OR (Cin AND (x XOR y)); END; CONFIGURATION adder_full_cfg OF adder_full IS FOR adder_full_arch END FOR; END CONFIGURATION; LIBRARY IEEE; use IEEE.std_logic_1164.all; ENTITY adder_full IS PORT (x, y, Cin: IN std_logic; Sum, Cout: OUT std_logic ); END;

9 CWRU EECS 317 Starting Synopsys environment if remote: telnet five.eecs.cwru.edu note: you can have several telnets from your computer logon if local: Open a console window if local: click rightmost mouse button, select hosts, then this host Start typing within the console window Start the cshell: /bin/csh Change your directory to Synopsys: cd ~/SYNOPSYS Source the synopsys executable paths and environment source /local/eda/synopsys_setup.csh

10 CWRU EECS 317 VHDL analyzer: vhdlan For example: > vhdlan –NOEVENT adder_full.vhd Synopsys 1076 VHDL Analyzer Version 2000.06--May 24, 2000 Copyright (c) 1990-2000 by Synopsys, Inc. ALL RIGHTS RESERVED This program is proprietary and confidential information of Synopsys, Inc. and may be used and disclosed only as authorized in a license agreement controlling such use and disclosure. The vhdl analyzer analyzes the the vhdl for syntax errors Unix command: vhdlan –NOEVENT Must be done to every vhdl file in the design

11 CWRU EECS 317 Synthesis: Debugging syntax errors Use the editor in telnet host #1 to to fix the errors then write (:w) then in telnet host #2 type !vh to reanalyze the vhdl source code until there are no more errors. Open another telnet host terminal #2 (or telnet) window and run vhdlan for syntax errors. vhdlan –NOEVENT adder_full.vhd Open another telnet host terminal #2 (or telnet) window and run vhdlan for syntax errors. vhdlan –NOEVENT adder_full.vhd Open a telnet host terminal #1 (or telnet) window and Enter the generic_mux.vhd using an ascii editor: vi adder_full.vhd i--i for insert mode ….--enter code ESC--Escape key to exit insert mode :w--write the file but do not exit Open a telnet host terminal #1 (or telnet) window and Enter the generic_mux.vhd using an ascii editor: vi adder_full.vhd i--i for insert mode ….--enter code ESC--Escape key to exit insert mode :w--write the file but do not exit

12 CWRU EECS 317 VHDL Simulator: vhdlsim Unix command: vhdlsim Starts the text based vhdl simulator For example: > vhdlsim adder_full_cfg Synopsys 1076 VHDL Simulator Version 2000.06-- May 24, 2000 Copyright (c) 1990-2000 by Synopsys, Inc. ALL RIGHTS RESERVED This program is proprietary and confidential information of Synopsys, Inc. and may be used and disclosed only as authorized in a license agreement controlling such use and disclosure. # Simulator command line prompt #

13 CWRU EECS 317 VHDL Simulator list components: ls vhdlsim list command: ls [–type] [–value] lists the vhdl component types and data values # ls –type ADDER_FULLCOMPONENT INSTANTIATION STATEMENT STANDARDPACKAGE ATTRIBUTESPACKAGE STD_LOGIC_1164PACKAGE _KERNELPROCESS STATEMENT # # ls ADDER_FULL STANDARD ATTRIBUTES STD_LOGIC_1164 _KERNEL After reading in the adder_full.vhd design, a list will show

14 CWRU EECS 317 VHDL Simulator change directory: cd and pwd # ls –type XIN PORT type = STD_LOGIC YIN PORT type = STD_LOGIC CININ PORT type = STD_LOGIC SUMOUT PORT type = STD_LOGIC COUTOUT PORT type = STD_LOGIC _P0PROCESS STATEMENT # cd ADDER_FULL # pwd /ADDER_FULL vhdlsim cd command:cd cd.. pwd cd - change design hierarchy (cd.. go up a level) pwd - display present working directory Alternately, using full paths # ls –type /ADDER_FULL Alternately, using full paths # ls –type /ADDER_FULL

15 CWRU EECS 317 VHDL Simulator assign signal: assign # assign ‘1’ X # ls –value X'U' Y'U' CIN'U' SUM'U' COUT'U' vhdlsim command: assign [–after ] assign a value to a signal # ls –value X'1' Y'U' CIN'U' SUM'U' COUT'U' Alternately, using full paths # assign ‘1’ /ADDER_FULL/X Alternately, using full paths # assign ‘1’ /ADDER_FULL/X

16 CWRU EECS 317 VHDL Simulator run simulation: run # run # assign '1’ X # assign '1' Y # assign '0' Cin # ls –value X'1' Y'1' CIN'0' SUM'U' COUT'U' vhdlsim command: run [ ] Use Control-C to cancel a simulation # ls –value X'1' Y'1' CIN'0' SUM ’0' COUT’1' This is what we would expect

17 CWRU EECS 317 VHDL Simulator include vhdlsim command: include [-e] Reads and executes vhdlsim commands from a file -e will displays the lines as it reads them in cd ADDER_FULL assign '1' X assign '1' Y assign '0' Cin ls –value >adder_full.run run ls –value >>adder_full.run exit cd ADDER_FULL assign '1' X assign '1' Y assign '0' Cin ls –value >adder_full.run run ls –value >>adder_full.run exit For example, the file adder_full.vhdlsim contains: > overwrite file >> append to file

18 CWRU EECS 317 VHDL Simulator include using full path names assign '1’ /ADDER_FULL/X assign '1' /ADDER_FULL/Y assign '0' /ADDER_FULL/Cin ls –value /ADDER_FULL >adder_full.run run ls –value /ADDER_FULL >>adder_full.run exit assign '1’ /ADDER_FULL/X assign '1' /ADDER_FULL/Y assign '0' /ADDER_FULL/Cin ls –value /ADDER_FULL >adder_full.run run ls –value /ADDER_FULL >>adder_full.run exit For example, adder_full.vhdlsim using full path names:

19 CWRU EECS 317 VHDL Simulator trace vhdlsim command: trace Traces vhdl signals on GUI Synopsys Waveform Viewer To best view signals a time element must be added Use View => Full Fit in order to fully view the signals cd ADDER_FULL assign –after 5 '1’ X assign –after 5 '1’ Y assign –after 5 '0' Cin trace X Y Cin Sum Cout ls –value run ls –value exit cd ADDER_FULL assign –after 5 '1’ X assign –after 5 '1’ Y assign –after 5 '0' Cin trace X Y Cin Sum Cout ls –value run ls –value exit For example,

20 CWRU EECS 317 VHDL Simulator: abstime, step, next, status vhdlsim command: abstime display the current absolute simulation time so far vhdlsim command: step [ ] step through each vhdl statement, default n=1 vhdlsim command: next [n steps] step through each vhdl statement within current arch vhdlsim command: status show current simulation status

21 CWRU EECS 317 VHDL Simulator: where, environment, restart vhdlsim command: where displays where the process and event stacks vhdlsim command: environment displays the simulator environmental variables vhdlsim command: restart restart the simulation using all previous commands Clean restart: restart /dev/null

22 CWRU EECS 317 VHDL Simulator: help vhdlsim command: help [ ] simulator command help: help ls # help step Subject:STEP Syntax:STEP [n] STEP executes the next "n" lines of VHDL source code. If you omit the argument "n", it executes a single line. STEP enters functions and procedures. STEP does not count or stop on lines that are monitored by an OFF monitor.

23 CWRU EECS 317 VHDL Simulator: unix shell, exit, quit, slist vhdlsim command: ! Execute a unix shell command: !ls vhdlsim command: slist [entity name] display the current source or entity name read in vhdlsim command: quit quit the simulator vhdlsim command: exit exit the simulator

24 CWRU EECS 317 adder_full_tb.vhd: full adder test bench ENTITY adder_full_tb IS PORT (Sum, Cout:OUT std_logic); END; ENTITY adder_full_tb IS PORT (Sum, Cout:OUT std_logic); END; LIBRARY IEEE; use IEEE.std_logic_1164.all; adder_full.vhd adder_full_tb.vhd Stimulus Only Test Bench Entity The output of the testbench will be observe by the digital waveform of the simulator.

25 CWRU EECS 317 ARCHITECTURE adder_full_tb_arch OF adder_full_tb IS COMPONENT adder_full PORT (x, y, Cin: IN std_logic; Sum, Cout: OUT std_logic); END COMPONENT; SIGNAL x, y, Cin: std_logic; BEGIN x <= '0', '1' after 50 ns, '0' after 100 ns; --Test Input y <= '1', '1' after 50 ns, '0' after 100 ns; Cin <= '0', '1' after 50 ns; UUT_ADDER: adder_full PORT MAP(x, y, Cin, Sum, Cout); END; adder_full_tb.vhd: architecture CONFIGURATION adder_full_tb_cfg OF adder_full_tb IS FOR adder_full_tb_arch END FOR; END CONFIGURATION;

26 CWRU EECS 317 VHDL Simulator: test bench # ls ADDER_FULL_TB STANDARD ATTRIBUTES STD_LOGIC_1164 _KERNEL # cd ADDER_FULL_TB # ls SUM _P0 _P2 ADDER_FULL Y COUT _P1 UUT_ADDER X CIN # ls –type SUM OUT PORTtype = STD_LOGIC COUTOUT PORTtype = STD_LOGIC UUT_ADDERCOMPONENT INSTANTIATION ADDER_FULLCOMPONENT X SIGNALtype = STD_LOGIC Unix> vhdlan –NOEVENT adder_full.vhd Unix> vhdlan –NOEVENT adder_full_tb.vhd Unix> vhdlsim adder_full_tb_cfg

27 CWRU EECS 317 VHDL Simulator: run 10 ns # ls –value SUM'U' COUT'U' X'U' Y'U' CIN'U' # run 10 10 NS # ls –value SUM'1' COUT '0' X '0' Y '1' CIN'0' # ls –value SUM'U' COUT'U' X'U' Y'U' CIN'U' # run 10 10 NS # ls –value SUM'1' COUT '0' X '0' Y '1' CIN'0'

28 CWRU EECS 317 VHDL Simulator: run 60 ns (go passed 50ns) # run 60 70 NS # ls –value SUM '1' COUT '1' X'1' Y'1' CIN'1’ # quit # run 60 70 NS # ls –value SUM '1' COUT '1' X'1' Y'1' CIN'1’ # quit

29 CWRU EECS 317 VHDL Simulator GUI: vhdldbx Unix command: vhdldbx & Starts the VHDL GUI version of vhdlsim Does everything vhdlsim does via menus Use the trace command to view signals First mark the variable with the mouse Then traces -> signals

30 CWRU EECS 317 Assignment #3 (1/3) a) Test the vhdl code of assignment #2.3 1-bit alu and then run it using vhdlan and vhdlsim. Write a two useful test cases for each function (i.e. show one with carry and another without carry). Hand in the source files and session using the Unix script command (see next page). function fALU bit operation 000S = 0; Cout = 0 001S = x 010S = y; Cout =1; 011S = Cin; Cout = x 100S = x OR y; Cout=x; 101S = x AND y; Cout=x; 110(Cout, S) = x + y + Cin; (component) 111(Cout, S) = full subtractor (component) x ALU y C in f S C out

31 CWRU EECS 317 Assignment #3 (2/3) 1) logon… 2) /usr/bin/script assign3_a.txt 3) /bin/csh 4) cd ~/SYNOPSYS 5) source /local/eda/synopsys_setup.csh 6) cat alu_bit.vhd 7) vhdlan –NOEVENT alu_bit.vhd 8) vhdlsim alu_bit_cfg 9) …test bench commands “assign”,”ls -value”,... 10) exit 11) exit 12) lpr assign3_a.txt

32 CWRU EECS 317 Assignment #3 (3/3) b) Write a vhdl test bench to the vhdl code of 3a 1-bit alu and then run it using vhdlan and vhdlsim. Use the same test cases from part a. Hand in the source files and session using the Unix script command as follows: 1) logon… 2) /usr/bin/script assign3_b.txt 3) /bin/csh 4) cd ~/SYNOPSYS 5) source /local/eda/synopsys_setup.csh 6) cat alu_bit.vhd 7) cat alu_bit_tb.vhd 8) vhdlan –NOEVENT alu_bit.vhd 9) vhdlan –NOEVENT alu_bit_tb.vhd 10) vhdlsim alu_bit_tb_cfg 11) ….NO “assign” commands 12) exit 13) exit 14) lpr assign3_b.txt

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