1. Anasim Corporation Technology, Methodology, PI-FP Environment and Examples Raj Nair Sept. 22, 2008

2. September 2008 AnaSIM 2 Presentation Overview Background and history Background and history Methodology & technology fundamentals Methodology & technology fundamentals  - fp  - fp Customer chip / illustrative examples Customer chip / illustrative examples Floorplanning / optimization discussion Floorplanning / optimization discussion Tool demo (as possible) Tool demo (as possible) Key messages of interest Key messages of interest

3. September 2008 AnaSIM 3 Power Integrity Challenges: CPU Power doubles every ~36 months Transistors double every ~18 months Operating modes create load shifts Which create supply voltage ‘droops’ Managed by package devices (Original figure from C. Baldwin) Mother Board Capacitors Microprocessor Heat Spreader Package Substrate Pentium™ is a trademark of Intel® Corporation

4. September 2008 AnaSIM 4 Package CAP Loop-L scaling and gives Load shift induced voltage noise equation and derivation of package component characteristics scaling Inversely related to process scaling (on-die cap) & (freq. scaling) 2 65nm <<0.1pH! References: Nair 2001 Intel Assembly Technology Journal – Invited Paper on ‘Pathfinding’ 2002 Intel Technology Journal paper “Emerging Directions for Packaging…”Emerging Directions for Packaging

5. September 2008 AnaSIM 5 On-die L & L*di/dt challenge References: Nair, Nair & Bennett, 2008 EDADesignline® publications “A Power Integrity Wall follows the Power Wall” & “Dynamic Voltage Droops & Total PI”A Power Integrity Wall follows the Power WallDynamic Voltage Droops & Total PI

6. September 2008 AnaSIM 6 Challenge Atomic or Abstract? Atomic or Abstract? Analyze ripples by molecular interactions? Polygonal Analyses Polygonal Analyses Nanoscale IC’s face exploding, exponential computation complexity Energy & Efficiency Energy & Efficiency Must know IC’s ripples

7. September 2008 AnaSIM 7 Meeting the Challenge Differential Power Differential Power Voltage is a potential difference; treat power grid differentially Partition hierarchically & exploit symmetry ECD: Continuum models ECD: Continuum models Grid is uniform; treat as a voltage-continuum along a single surface USPTO PUBUSPTO PUB Include R, L, C and solve ‘true-electromagnetically’ Abstract silicon, package Abstract silicon, package Include distributed models for silicon loads, CAP, pkg and board components

8. September 2008 AnaSIM 8 Abstraction & Physics-based Sims High levels of Abstraction High levels of Abstraction Power GRID as SURFACE Power GRID as SURFACE DISTRIBUTED circuit load currents & capacitance DISTRIBUTED circuit load currents & capacitance SYMMETRY in physical as well as electrical aspects SYMMETRY in physical as well as electrical aspects Comprehensive Modeling Comprehensive Modeling All grid electromagnetic properties, R, L, C used All grid electromagnetic properties, R, L, C used Actual block load current profiles used; di/dt, load activity factors included Actual block load current profiles used; di/dt, load activity factors included Physics based Simulation Physics based Simulation Field solver employed for Maxwell’s equations on ‘surfaces’ / NO ‘models’ Field solver employed for Maxwell’s equations on ‘surfaces’ / NO ‘models’

9. September 2008 AnaSIM 9 On-Die CAP for Noise Reduction Simple, lumped SPICE analyses indicate On-Die CAP helps in ΔV CC reduction Area cost, Gate Oxide leakage are concerns Reference: Narendra, ICCAD ‘03

10. September 2008 AnaSIM 10 SoC Power Integrity Simulation Do CAPACITORS really absorb noise energy? 9 x 7mm chip 5nF /sq. cm distributed CAP 100mA peak noise pulse of 100ps width Power grid simulation Explicit CAP LENS Pulse noise source Differential noise R+L+C Dynamic Noise Simulation in  -fp Source: D. Bennett, ANASIM Corp.,  -fp power integrity aware floor planner, www.anasim.comwww.anasim.com Animation slide Use slide show

11. September 2008 AnaSIM 11 Single active circuit block in a 4x4mm IC   -fp what-if experiments showing effect of gate switching time and on-chip de-cap on maximum voltage droop. resonance Resonant effects; More / Less CAP?

12. September 2008 AnaSIM 12 PI-FP Tool Environment Simulation netlist.TRAN 200e-12.PLOT 20.ACC 0.0060.PRINTNODE ALL Ggrid1 0.2 0.2 0.0005 0.0080 0.030 10e-9 10e-9 Igrid1 0.1 0.1 0.02 0.02 pulse.txt 1 Ttline1 1 2 0.01 10e-9 100e-12 0.3 Ngrid1 1 0.11 0.11 pulse.txt : Current Source 0 22E-12 0.030901699 40E-12 0.058778525 60E-12 0.080901699 80E-12 0.095105652 100E-12 0.1 120E-12 0.095105652 140E-12 0.080901699 160E-12 0.058778525 180E-12 0.030901699 200E-12 0

13. September 2008 AnaSIM 13 PI-FP Tool Environment contd. Multi-Grid design Multi-Grid design L calculation L calculation Planar or 3D Planar or 3D Include multiple chips in stacked or planar design Include multiple chips in stacked or planar design Code efficiency Code efficiency Each GRID on its own core (CPU) Each GRID on its own core (CPU)

14. September 2008 AnaSIM 14 Non-disruptive, Complementary bridges PI gap Anasim’s  -fp bridges PI gap  -fp  Complements, not compete with or replace traditional IC analysis!  Win-Win-Win : User, EDA partner & Anasim  Optimization and front-end planning  Reduces cost : cuts on- chip or on-pkg CAP  Results in MINUTES Minimizes costly design iterations

15. September 2008 AnaSIM 15 Example: System-level Chip Sim GUI or Netlist capture GUI or Netlist capture Chip NETLIST Chip NETLISTNETLIST Load current profiles are pulse100gap100 and pulse200gap200 Load current profiles are pulse100gap100 and pulse200gap200 pulse100gap100 pulse200gap200 pulse100gap100 pulse200gap200 SYMMETRY in physical as well as electrical aspects SYMMETRY in physical as well as electrical aspects Experiment-1 results Experiment-1 results Chip grid ANIMATION & Mirror Chip grid ANIMATION & MirrorANIMATION MirrorANIMATION Mirror Notice substantial voltage variation of top left corner Notice substantial voltage variation of top left corner Cap 200pF added: results Cap 200pF added: results Chip grid ANIMATION & Mirror Chip grid ANIMATION & MirrorANIMATION MirrorANIMATION Mirror  -fp simulation schematic illustration (hyperlinked image)

16. September 2008 AnaSIM 16 Advanced SiP Simulation Near load systems Near load systems Active Noise Regulator* Active Noise Regulator* Distributed Local (POL) Voltage Regulators Distributed Local (POL) Voltage Regulators Spatial & Temporal Spatial & Temporal Power supply variation in x, y and t Power supply variation in x, y and t Data can feed into future Dynamic Timing Analysis? Data can feed into future Dynamic Timing Analysis? Simulation speed allows ‘what-if’ experiments for optimization Simulation speed allows ‘what-if’ experiments for optimization Chip power grid noise ANR attached to top left corner of grid Reference: * Nair & Bennett, ComLSIComLSI Power Management Designline article http://www.powermanagementdesignline.com/howto/175800373http://www.powermanagementdesignline.com/howto/175800373 Animation slide Use slide show

17. September 2008 AnaSIM 17 Customer Chip: CAP & Noise CAPACITOR blocks from IO ring corners connected into Core power grid increased noise in the core grid Corner CAPs connected to IO RingCorner CAPs connected to Core Grid Analysis on a CLOCK chip Source: ComLSI, Inc. www.comlsi.comwww.comlsi.com

18. September 2008 AnaSIM 18 IO Ring impact on Core Noise The voltage regulators, connecting between the IO Ring and the Core Grid are seen to become significant noise injection nodes with the inclusion of loads and the IO Ring. Pictures above are snapshots of dynamic plots. Analysis on a customer CLOCK chip

19. September 2008 AnaSIM 19 Customer chip Grid R, L + C Design  With fixed on-chip capacitance value, increase in grid wire width (reduction in resistance with minimal benefit in inductance) reduces noise to a point  Increase in capacitance on-die has sub-linear benefit in noise reduction; more CAP is not always good…

20. September 2008 AnaSIM 20 Power Gating & Noise Flow Source: ANASIM Corp.,  -fp power integrity aware floor planner, www.anasim.comwww.anasim.com Power Gating transforms preferred pathways for noise flow in addition to transient noise generation due to large switched capacitances… Animation slide

21. September 2008 AnaSIM 21 Floorplanning / Optimization GRID wire width, spacing, pitch GRID wire width, spacing, pitch Metal resource savings, routing / timing facilitation Metal resource savings, routing / timing facilitation DECAP optimization DECAP optimization Area savings Area savings Block placement tweaks for PI Block placement tweaks for PI Noise generation, propagation Noise generation, propagation Chip-Package co-simulation Chip-Package co-simulation Operating voltage (Energy) tuning Operating voltage (Energy) tuning Resonance detection and avoidance… Resonance detection and avoidance…

22. September 2008 AnaSIM 22 Anasim Info Incorprated in 2006 Incorprated in 2006 Spin-off from ComLSI (2003 incorporation) Spin-off from ComLSI (2003 incorporation) Analog, Mixed-Signal design services, consulting, IP in signaling and power management Analog, Mixed-Signal design services, consulting, IP in signaling and power management Core expertise: Power Integrity Core expertise: Power Integrity  -fp, PI methodology & consulting  -fp, PI methodology & consulting IP: Effective Current Density (ECD), pat. pend. IP: Effective Current Density (ECD), pat. pend. Vision Vision “Complete simulation through continuum models” “Complete simulation through continuum models” Total Power Integrity (TPI) inclusion into chip / system design Total Power Integrity (TPI) inclusion into chip / system design

23. September 2008 AnaSIM 23 Core Anasim Team (75 yrs+) CXO: Raj Nair CXO: Raj Nair Founded ComLSI in 2003, successfully creating, patenting and licensing Silicon IP (12 patents, 4 issued) in power integrity / multimedia data communications, 22+ years in industry & academia, 40+ total patents, prior corporate experience at Intel, Larsen & Toubro, ~6 years of low-burn- rate startup experience. Founded ComLSI in 2003, successfully creating, patenting and licensing Silicon IP (12 patents, 4 issued) in power integrity / multimedia data communications, 22+ years in industry & academia, 40+ total patents, prior corporate experience at Intel, Larsen & Toubro, ~6 years of low-burn- rate startup experience. Chief Scientist: Dr. Donald Bennett Chief Scientist: Dr. Donald Bennett Founded QuantumDA in 2003, developing RLCSim, GRID simulation suite, EDA Director at ComLSI, 15 years prior corporate experience in semiconductor device physics, IC design at ST Micro. Founded QuantumDA in 2003, developing RLCSim, GRID simulation suite, EDA Director at ComLSI, 15 years prior corporate experience in semiconductor device physics, IC design at ST Micro. GUI Architect: Malcolm White GUI Architect: Malcolm White 38+ years in semiconductor physical design and CAD software, Serial entrepreneur, ComLSI PD architect, corporate: Intel, Mentor. 38+ years in semiconductor physical design and CAD software, Serial entrepreneur, ComLSI PD architect, corporate: Intel, Mentor.

24. September 2008 AnaSIM 24 Milestones to-date Chip Floorplan ‘true-electromagnetic’ simulation Chip Floorplan ‘true-electromagnetic’ simulation Patent pending algorithm – ECD Patent pending algorithm – ECD Front-end chip floorplan optimization now feasible. Front-end chip floorplan optimization now feasible. Stand-alone Tool released to market (2008) Stand-alone Tool released to market (2008) GUI, Simulator, Input language, Results Viewer & DEMO GUI, Simulator, Input language, Results Viewer & DEMO Close to signing on a Japanese distributor Close to signing on a Japanese distributor Industry Validation ongoing Industry Validation ongoing Anasim white papers top three of EDA Designline’s highest user-rated papers; SoC2007, Nanotech 2008 and NanoEquity 2008 invited presentations Anasim white papers top three of EDA Designline’s highest user-rated papers; SoC2007, Nanotech 2008 and NanoEquity 2008 invited presentationshighest user-ratedhighest user-rated Compiling a book on Power Integrity (PI), Prentice Hall™ Compiling a book on Power Integrity (PI), Prentice Hall™

25. September 2008 AnaSIM 25 Summary Anasim bringing sea change into SoC methodology with physics-based analyses and high levels of abstraction Anasim bringing sea change into SoC methodology with physics-based analyses and high levels of abstraction Benefits to chip resource usage, area, energy, performance, and total design effort Benefits to chip resource usage, area, energy, performance, and total design effort Non-disruptive, Win-Win-Win engagement Non-disruptive, Win-Win-Win engagement Fills the GAP in Total Power Integrity analyses Fills the GAP in Total Power Integrity analyses Links, tel. raj@anasim.com +1 480-694-5984 Links, tel. raj@anasim.com +1 480-694-5984raj@anasim.com Anasim White Papers pifp1.pdf, pifp2.pdf, pifp3.pdf Anasim White Papers pifp1.pdf, pifp2.pdf, pifp3.pdf Anasimpifp1.pdfpifp2.pdfpifp3.pdf Anasimpifp1.pdfpifp2.pdfpifp3.pdf Product -  -fp brochure Product -  -fp brochure  -fp brochure  -fp brochure ComLSI, parent co. ComLSI, parent co.parent coparent co