1. Modeling and Estimation of Full-Chip Leakage Current Considering Within- Die Correlations Khaled R. Heloue, Navid Azizi, Farid N. Najm University of Toronto {khaled,nazizi,najm}@eecg.utoronto.ca

2. 2 Introduction n Leakage current has been increasing and, in some cases, has become the design limiter n Statistical process variations (mainly L and V th ) make leakage statistical in nature l Interested in the mean and variance of the chip leakage l Leakage is also state-dependent, but not too strongly so n Large leakage variance leads to chip yield loss l Performance may vary by 30% but leakage varies by 5X l Thus, leakage may become more yield-limiting than delay n During process & chip design, we need to control the leakage spread, i.e., to minimize the leakage variance

3. 3 Low-Leakage Design n By design: l process development l Body-bias l Sleep transistors and multiple voltage islands l Low-leakage libraries (circuit design) l Drowsy states, etc. n Most of this is standard practice today n How can EDA help further manage the leakage? l EDA should be able to accurately model and estimate full-chip leakage statistics to empower low-leakage design l This option should be available at an early or a late stage of design

4. 4 Background n Full-chip leakage estimation is useful at different points in the design flow: l Early estimation: given limited information about the design u Useful for design planning (power budgeting) l Late estimation: complete netlist, possibly circuit placement u Useful for final sign-off n Work on “early estimation”: l Narendra et al. & Rao et al. u Did not handle logic-gate/transistor topologies and/or within-die correlation n Work on “late estimation”: l Chang et al. & Agarwal et al. u O(n 2 ) complexity (some refinements at the expense of accuracy)

5. 5 Full-chip Leakage Model n We propose a “Full-chip Leakage Estimation Model” that considers: l Logic-gate structures and transistor topologies l Die-to-Die & Within-Die variations l Within-Die correlation n Our model has the following features: l Accurate l Computationally efficient (constant-time) l Can be used early or late in the design flow

6. 6 Hypothesis n Hypothesis: l Certain “high-level characteristics” of a candidate chip design are sufficient to determine its leakage statistics l All designs that share the same values of these high-level characteristics have approximately the same leakage, for large gate count n Hypothesis confirmed by results

7. 7 High-level Characteristics

8. 8 Early Estimation vs Late Estimation n Whether in Early or Late modes, the inputs to our model are the same l Shown in previous slide n Only difference is how the “Design Information” is obtained: l In Early mode: u number of gates, frequency of cell usage, and dimension of layout are either “specified” or “expected” based on design experience l In Late mode: u number of gates, frequency of cell usage, and dimension of layout are “extracted” from the fully specified design

9. 9 Process Information n We focus on leakage variations due to channel length (L) variations l The effect of V th variations on the leakage mean is known (multiplicative term) l The effect of V th variations on the leakage variance is negligible compared to L n We assume that the mean (μ) and standard deviation (σ) of L are known n Die-to-die and within-die variances of L are also known σ 2 = σ 2 dd + σ 2 wd

10. 10 Process Information n Channel length L variations are correlated due to: l Die-to-die (D2D) variations are totally correlated l Within-die (WID) variations are spatially correlated We assume that the WID correlation function,  (r), for L is known l It gives the correlation coefficient between the lengths of two devices separated by a distance r n Total length correlation (D2D + WID) can be easily obtained

11. 11 Correlation Function

12. 12 Library Information n Our leakage model works for standard cell type designs l A library of p standard cells is available n Characterize every cell in the library for leakage (mean and variance) using one of two methods: l Monte-Carlo (MC) analysis, by varying L u Good accuracy, costly l Analytical method, by fitting leakage (X) into functional form, and determine analytically the exact leakage mean and variance u Less accurate, cheap n Result: mean (μ i ) and standard deviation (σ i ) of leakage for every cell in the library, i = 1, …, p

13. 13 Leakage Fitting – “Good”

14. 14 Leakage Fitting – “bad”

15. 15 Histogram: MC vs Analytical

16. 16 Leakage Correlation n We previously assumed that channel length correlation is available from the foundry n What about leakage correlation? l Leakage correlation depends on: u Distance separating cells u Types of cells n Using the fitted functional form for cell leakage: l We can determine analytically the leakage correlation between gates of types m and n, where m,n = 1, …, p, given channel length correlation. We call it a mapping f m,n (.)

17. 17 Leakage Correlation: MC vs Analytical n For all pairs of cells (m,n), we found that leakage correlation is approximately equal to the channel length correlation

18. 18 Design Information n Information about the actual design: l Expected/extracted number of cells in the design u n cells l Expected/extracted frequency of usage of cells in the library u for cell i, α i = n i /n l Expected/extracted dimensions of the layout area (chip core) u Width W and Height H

19. 19 Full-chip Model n The full-chip model l a rectangular array of dimensions H and W l n identical sites, where n is the total number of gates l Each site is occupied by a Random Gate (RG) n What is a Random Gate?

20. 20 Random Gate n Similar to a RV, a RG takes as instances or outcomes gates from the standard-cell library n We require the discrete probability distribution of the RG to be identical to the frequency of cell usage l P{ RG = gate i } = α i for i = 1, …, p n Based on the RG, the Full-chip model is a template for all designs that share the same high-level characteristics l It covers the set of all such designs (recall hypothesis) l We’ll show that this set converges (in terms of leakage)

21. 21 Leakage of RG n If the leakage statistics of the RG are defined, Full-chip leakage estimation is possible l Need: mean, variance, and correlation (or covariance) of RG n These will depend on: l Frequency of cell usage (design information) l means and variances of leakage of cells (library information) l Channel length and Leakage correlation (process information)

22. 22 Leakage of RG n Mean: n Variance: n Covariance:

23. 23 Full-chip Leakage Estimation n Recall the full-chip model is as an array of generic “sites” to be occupied by RGs n We determined the mean, variance, and correlation of the RG leakage Call them μ,  2, and  (r) n Then we can determine the full-chip leakage mean and variance

24. 24 Full-chip Leakage Estimation Assume that  (r) goes to zero at a distance D where D is less than the chip core height H and width W l Focus on within-die variations, for simplicity of presentation n Let P be the chip core perimeter, and A its area n Let d be the logic gate density per unit area (e.g. n/A) n Then, the full-chip leakage mean and variance are given by:

25. 25 Full-Chip Leakage Estimation

26. 26 Confirming Hypothesis: Test plan n Consider a range of target gate counts n For a given # gates l Generate many circuits that share the same high-level characteristics (satisfy the cell usage frequencies, etc…) l For each circuit u Place it u Use Monte Carlo on parameters to generate leakage distribution u Measure the error in mean and standard deviation relative to our estimate (Integral) l Find the maximum/min error over all circuits l Plot the two error extremes against that gate count n See plot on next slide

27. 27 Results

28. 28 Confirming Hypothesis n Two conclusions from plot: l First, the high-level characteristics of a design (which drive our model) are sufficient to determine accurately its leakage statistics l Second, the set of (possibly different) designs that share the same high-level characteristics have approximately the same leakage, for large gate count n Note that this is an example of early estimation (high-level characteristics were specified a priori)

29. 29 Late Estimation n We have also tested our model as a full-chip leakage late estimator l Synthesized, placed, and routed ISCAS85 benchmark circuits l Extracted the sufficient high-level characteristics l Used our model to predict leakage and compared results to MC sampling u Listed error in standard deviation (error in mean is negligible) c499c1355c432c1908c880c2670c5315c7552c6288 1.04%0.41%1.14%0.36%0.74%0.52%0.23%0.34%1.38%

30. 30 Conclusion n Full-chip leakage estimation is possible both at an Early or a Late stage: l Based on concept of Random Gate l Has been verified for standard-cell type layouts l For large gate count, accuracy is very good n High-level characteristics of design are all that matters: l Standard Cell leakage mean and variance l Cell usage frequencies l Leakage correlation function l Chip core area and perimeter (dimensions) l Number of cells in the design n Further work is required to handle both timing and leakage in a single estimator

31. 31 Bibliography n Siva Narendra, Vivek De, Dimitri Antoniadis, and Anantha Chandrakasan. Full-chip sub-threshold leakage power prediction model of sub-0.18μm CMOS. IEEE/ACM International Symposium on Low Power Electronics and Design, 2002. n Rajeev Rao, Ashish Srivastava, David Blaauw, and Dennis Sylvester. Statistical analysis of sub-threshold leakage current for VLSI circuits. IEEE Transactions on VLSI Systems, 12(2):131–139, February 2004. n Hongliang Chang and Sachin S. Sapatnekar. Full-chip analysis of leakage power under process variations, inlcuding spatial correlations. IEEE Design Automation Conference, 2005. n Amit Agarwal, Kunhyuk Kang, and Kaushik Roy. Accurate estimation and modeling of total chip leakage considering inter-& intra-die process variations. IEEE International Conference on Computer-aided Design, 2005.