1. Modern VLSI Design 4e: Chapter 2 Copyright  2009 Prentice Hall PTR Topics n Derivation of transistor characteristics.

2. Modern VLSI Design 4e: Chapter 2 Copyright  2009 Prentice Hall PTR MOSFET gate as capacitor n Basic structure of gate is parallel-plate capacitor: gate substrate SiO 2 x ox VgVg + -

3. Modern VLSI Design 4e: Chapter 2 Copyright  2009 Prentice Hall PTR Parallel plate capacitance n Formula for parallel plate capacitance: C ox =  ox / x ox n Permittivity of silicon:  ox = 3.46 x 10 -13 F/cm 2 n Gate capacitance helps determine charge in channel which forms inversion region.

4. Modern VLSI Design 4e: Chapter 2 Copyright  2009 Prentice Hall PTR Threshold voltage Components of threshold voltage V t : n V fb = flatband voltage; depends on difference in work function between gate and substrate and on fixed surface charge.  s = surface potential (about 2  f ). n Voltage on paralell plate capacitor. n Additional ion implantation.

5. Modern VLSI Design 4e: Chapter 2 Copyright  2009 Prentice Hall PTR Body effect n Reorganize threshold voltage equation: V t = V t0 +  V t n Threshold voltage is a function of source/substrate voltage V sb. Body effect  is the coefficienct for the V sb dependence factor.

6. Modern VLSI Design 4e: Chapter 2 Copyright  2009 Prentice Hall PTR Example: threshold voltage of a transistor V t0 = V fb +  s + Q b /C ox + V II = -0.83 V + 0.58 V + (1.4E-8/8.6E-7) + 0.93 V = 0.7 V Body effect  n = sqrt(2q  Si N A /C ox ) = 0.1  V t =  n [sqrt(  s + V sb ) - sqrt(V s )] = 0.05 V

7. Modern VLSI Design 4e: Chapter 2 Copyright  2009 Prentice Hall PTR More device parameters Process transconductance k’ =  C ox. Device transconductance  = k’W/L.

8. Modern VLSI Design 4e: Chapter 2 Copyright  2009 Prentice Hall PTR Channel length modulation length parameter describes small dependence of drain corrent on V ds in saturation. n Factor is measured empirically. n New drain current equation: –I d = 0.5k’ (W/L)(V gs - V t ) 2 (l  - V ds ) n Equation has a discontinuity between linear and saturation regions---small enough to be ignored.

9. Modern VLSI Design 4e: Chapter 2 Copyright  2009 Prentice Hall PTR Gate voltage and the channel gate drainsource current IdId V ds < V gs - V t gate drainsource current IdId gate drainsource IdId V ds = V gs - V t V ds > V gs - V t

10. Modern VLSI Design 4e: Chapter 2 Copyright  2009 Prentice Hall PTR Leakage and subthreshold current n A variety of leakage currents draw current away from the main logic path. n The subthreshold current is one particularly important type of leakage current.

11. Modern VLSI Design 4e: Chapter 2 Copyright  2009 Prentice Hall PTR Types of leakage current. n Weak inversion current (a.k.a. subthreshold current). n Reverse-biased pn junctions. n Drain-induced barrier lowering. n Gate-induced drain leakage; n Punchthrough currents. n Gate oxide tunneling. n Hot carriers.

12. Modern VLSI Design 4e: Chapter 2 Copyright  2009 Prentice Hall PTR Subthreshold current n Subthreshold current: –Isub = ke [(Vgs - Vt)/(S/ln 10)] [1-e -qVds/kT ] n Subthreshold slope S characterizes weak inversion current. n Subthreshold current is a function of V t. –Can adjust V t by changing the substrate bias to control leakage.

13. Modern VLSI Design 4e: Chapter 2 Copyright  2009 Prentice Hall PTR Thermal effects n Vicious cycle: –Leakage current causes heating. –Heating increases leakage current. n Thermal runaway: chip overheats due to leakage. n Subthreshold leakage current is most important temperature-dependent current. –8x-12x per 100°C.

14. Modern VLSI Design 4e: Chapter 2 Copyright  2009 Prentice Hall PTR Circuit simulation n Circuit simulators like Spice numerically solve device models and Kirchoff’s laws to determine time-domain circuit behavior. n Numerical solution allows more sophisticated models, non-functional (table- driven) models, etc.

15. Modern VLSI Design 4e: Chapter 2 Copyright  2009 Prentice Hall PTR Some (by no means all) Spice model parameters L, W : transistor length width. KP : transconductance. GAMMA : body bias factor. AS, AD : source/drain areas. CJSW : zero-bias sidewall capacitance. CGBO : zero-bias gate/bulk overlap capacitance.