1. Sub-threshold Design of Ultra Low Power CMOS Circuits Students: Dmitry Vaysman Alexander Gertsman Supervisors: Prof. Natan Kopeika Prof. Orly Yadid-Pecht Alexander Belenky Annual Projects Conference July 2nd, 2008

2. 2/7/2008 Alexander Gertsman Dmitry Vaysman 2 Motivation for Power Reduction in CMOS circuits 4004 8008 8080 8085 8086 286 386 486 Pentium® P6 1 10 100 1000 10000 19701980199020002010 Year Power Density (W/cm 2 ) Hot Plate Nuclear Reactor Rocket Nozzle Sun’s Surface Source: Intel Medical devices Micro sensors Portable electronics Low/Medium Performance Applications

3. 2/7/2008 Alexander Gertsman Dmitry Vaysman 3 Some Trends – Vdd, V T, Energy/Operation Source: www.intel.com Sources: Mary Jane Irwin course, ITRS roadmap for semiconductors

4. 2/7/2008 Alexander Gertsman Dmitry Vaysman 4 Some Trends – Subthreshold Leakage - Sub-threshold leakage power as a percentage of total power, and it is already approaching the practical limit of 50% - “When this leakage power is about 50% of total power, further supply voltage scaling does not make sense” (Intel, 2006) Sub-threshold leakage power Source: www.intel.com Sub-threshold leakage power as a percentage of total power Source: www.intel.com

5. 2/7/2008 Alexander Gertsman Dmitry Vaysman 5 I5I5 I1I1 I2I2 I3I3 I4I4 I6I6 The most significant component of the I OFF is the Sub-Threshold current. V T =threshold voltage ζ = DIBL coefficient η = sub-threshold slope factor V th = thermal voltage Instead of fight it we use it! Transistor Leakages I 2 – Sub-threshold current. I 1 – pn junction Reverse I 3 – Tunneling into gate oxide I 4 – Hot carriers injection I 5 – Gate Induced Drain Leakage (GIDL) I 6 – Punchthrough

6. 2/7/2008 Alexander Gertsman Dmitry Vaysman 6 Sub-threshold benefits - C L is the loading capacitance - f CLK is the clock frequency - α is the activity factor Reduce the switching component by 4 to 81 times!!! Reduce the I SC leading to “double reduction”: lower V DD and lower I SC Reduce leakage power by 2.5 to 9 times. - I SC Short circuit current Reducing V DD to a sub-threshold levels will: - I leak Leakage current In total it gives us a reduction of leakage power by 5 to 90 times!!! - P sw is the switching (dynamic) power consumption - P sc is the short-circuit consumption - P leak is the leakage power consumption

7. 2/7/2008 Alexander Gertsman Dmitry Vaysman 7 Does subthreshold operation is the right way to go? VTC of CMOS 90nm Inverter Vdd [mV]Temp V IL [mV] V oH [mV] V IH [mV] V oL [mV] NML [mV] NMH [mV] 308.571 12598.1291.7159.32573.1132.4 25108.429816019.289.2138 -40116.2301.316215.8100.4139.3 Static Power consumption of CMOS 90nm Inverter Good noise margins

8. 2/7/2008 Alexander Gertsman Dmitry Vaysman 8 Innovation -Operation of the MOS transistor in the sub-threshold region is something that most designers try to eliminate. -We want to employ the sub-threshold leakage and make our circuit work at this area. -Develop methodologies for sub-threshold logic circuits design. -Investigate the most appropriate logic style for operation in the sub- threshold regime.

9. 2/7/2008 Alexander Gertsman Dmitry Vaysman 9 Simulation results -Ring oscillator Ring oscillator setup GateTransistor type VDD 200mV VDD 320mV VDD 1V Invertertyp4.4MHz58.7MHz7.7GHz hvtNR 7.7GHz lvt4.4MHz58.7MHz7.7GHz Oscillation frequencies Inverter based ring oscillator Total energy of ring oscillator

10. 2/7/2008 Alexander Gertsman Dmitry Vaysman 10 Simulation results –Sequential Circuit Four stages 90nm shift register implemented in three different topologies. Basic FF circuits: Test Circuit

11. 2/7/2008 Alexander Gertsman Dmitry Vaysman 11 Simulation results –Sequential Circuit Cont’ It Works!!! Time domain simulation result Average power consumption of SR Time domain simulation represents 200mV operation voltage and 500KHz Clk. Power dissipation of SR is 55nW when operated with 200mV.

12. 2/7/2008 Alexander Gertsman Dmitry Vaysman 12 Future Steps - Research different logic families. - To build generic test circuit. - Operate this test bench with different activity factors. - Evaluate minimum energy point. - Develop methodology for minimum energy point operation. - Test chip fabrication and results verification. - Fitting transistor models for sub-threshold operation. - Create basic logic cells library.

13. 2/7/2008 Alexander Gertsman Dmitry Vaysman 13 Any questions?