1. ECE 7366 Advanced Process Integration Set 8: Junctions and Contacts Dr. Wanda Wosik Text Book: B. El-Karek, “Silicon Devices and Process Integration” 1

2. Leakage in sub 32/28nm devices Yuri Erokhin, IWJT, 2012 Arghavani&M’saad, SST Scaling Issues Related to Source and Drain Regions Extensions: Ultra shallow junctions (USJ) with low Rs Doping: Ion Implantation Epi, Plasma Doping Monolayer Doping Annealing: Flash, Laser (no melt),  waves Compatibility with high K/Metal gate Contacts: Silicides with low contact resistance R co and low resistivity Si or SiGe consumption and device compatibility: Small  avoid leakage currents Dual workfunction for NMOS and PMOS with one silicide only Annealing: Low T  Compatibility with high K/Metal gate Line widths and structures control Fabrication of junctions and contacts must be optimized to limit defects  leakage  Parasitic resistances 2 Defect Free Junctions/Contacts

3. 3 Flash annealing - ramp to intermediate T (≈ 800 ˚C) then msec flash to high T (≈ 1300 ˚C). Recent flash annealing results with boron are much better than RTA. = flash data points Annealing must ensure shallow depths but also dopant activation and defects annealing. Overall, the shallow junction problem seems manageable through process innovation: both doping/deposition/implantation and annealing. Furnace, T= 550-700°C Solid Phase Epitaxial Regrowth (SPER) RTA, 1000-1100°C,, t<10s Spike Anneal, 1000-1100°C, ~1s Flash, 1100-1300°C, t<1ms Future Projections - Shallow Junctions Laser, 1100-1300°C, t<1ms

4. 4 Junction-Contact Integration in Scaled Down Devices The main component of parasitic resistance is due to contact/junction interface  limited dopant concentrations at the surface (solubility and activation), high energy barrier. We will see that junction contact integration also important in nonplanar bulk and SOI devices. 

5. 5 Real Numbers and Real Constrains for Junctions/Contacts from ITRS

6. 6 R. Jammy, Sematech MLD Cryo II

7. 7 3 Main Sources Areas Of Device Leakage Gate Leakage –High-k/Metal Gate reduce gate leakage by >1,000x Source Drain Leakage –Engineer the location of EOR damage to reduce junction leakage Gate Edge Leakage –Extension/HALO junction leakage influenced by band to band tunneling, HALO dose, extension abruptness and shallow EOR damage Borland et al. J.O.B. Technology (Strategic Marketing, Sales & Technology) Surdeanu et al, Philips/IMEC, SSDM 2004, Sept. 04

8. Resistance is Important so is the Leakage (defects) Borland et al., SST 8 Preamorphization (Ge, Si) before ion implantation Alleviates channeling effects Improves dopant activation after annealing Typically causes End of Range Defects (EOR) Optimization of Implantation: Cryogenic II to prevent in-situ annealing Molecular implants = clusters of ions Control the location of EOR with respect to junction depths C implant 5keV, 10 15 cm -2 Y. Erokhin, IWJT 2012 Crystal degradation and trapping of dopants at EOR Recrystallization depends on location for given annealing technology

9. 9 Cryogenic Ion Implantation (high dose C or Si) for P-doped layers Defect Engineering: The goal is to have high activation, shallow P-doped layers w/o crystallographic defects both in Si and strained Si-C layers. Itokawa et al. IEEE 2012

10. 10 Cryo-C co-Implants Effects in P & B Doping Yako et al. IWJT, 2011

11. 11 Leakage: Ion Implantation and Annealing

12. 12 Resistance: Ion Implantation and Annealing

13. J. Appl. Phys. 111, 044508 (2012) B concentration profiles for in situ doped and additionally B implanted poly-Si films with various annealing conditions. Solid lines represent simulated profiles Poly_silicon Sources B Segregation To Grain Boundaries And Diffusion In Polycrystalline Si Elevated (Raised) S/D Similar concept will be used with silicides  13

14. PMOS device final 2D activated B profile simulation of B beam-line implant with an energy/dose of 2keV/5°—10 15 /cm2. NMOS device final 2D activated As profile simulation of As beam-line implant with an energy/dose of 10keV/8°— 10 15 /cm2. 14 Raised S/D

15. Contacts to S/D Regions: Silicides with Low R co Rectifying vs Ohmic Contacts Work function in metals  m Barrier height Ohmic contact Schottky diode 15

16. Ideal and Experimental Barriers of M-S Contacts 4.05eV So the barrier height  b for Al-n-Si should be about 0.2 eV but when measured it is much higher ≅ 0.5 – 0.9 eV Surface states at the M-Si interface Very thin interfacial layer (may due to a physical layer) 16

17. Surface Charges Present at the Si Surface Large charge concentrations due to surface states in Silicon Zero charges Negative charges Positive charges 17

18. Fermi Level Pinning at the Charge Neutrality Distribution Point Barrier height becomes independent on metal used for contact but instead it depends on silicon charges (density of states=D it ). or Ideal Schottky 18

19. Image Force Barrier Lowering Image charge in the metal of opposite sign is created by an approaching electron - image potential Barrier at the M-Si interface is lowered by  Example: E=10 5 V/cm, x m ≅ 1.75 nm, and  ≅ 35 mV The barrier increases with + bias and decreases with – bias. Built-in voltage 19

20. Current Voltage Characteristics Forward Bias decreases the barrier at the semiconductor site A – Richardson constant; use m* For electrons A* ≅ 120 A/cm 2 K 2 For holes A* ≅ 32 A/cm 2 K 2 [A/cm 2 ] [A/cm 2 K 2 ] where Thermionic emission depends on barrier height Under the applied bias V F [A/cm 2 ] Electrons from metal Electrons from Si Barrier height important! 20

21. Current Voltage Characteristics Reverse Bias  increases the barrier at the semiconductor site j R =-j s (like in a p-n junction) decreases the barrier height  B by  x m ) so the reverse current: To reduce the field effect use guard rings To reduce parasitic resistance use n+ buried layer 21

22. Comparison Between Schottky Diode and p-n Junction SBD is majority-carrier non-injecting diode High switching speed device 22

23. Comparison Between Schottky Diode and p-n Junction Minority carrier injection and charge storage at high + bias voltages: Band bending at Si surface – holes>electrons (inversion) may be important at high currents (seen when voltage drops on resistance). Minority carrier current increases Charge storage of minority carriers reduces the switching speed  is the surface recombination velocity beneath the contact Faster speed for the Schottky diodes and smaller forward bias voltage 23

24. Capacitance-Voltage Measurements As for p-n junctions C depends on depletion thickness. Barrier extracted 24

25. Ohmic Contacts R Practical realization 25

26. 26 Contacts - Electrical Parameters thermionic emission Schottky = rectifying Tunneling Surface states in Si pin F-level deep in the E-gap no metal gives  B for n – Si contact resistance & rectifying contact thermionic emission Tunneling contact Thickness of depletion = tunneling layer 2.5 nm results from N d =6. 10 19 cm -3 contact area Depends on metal/semiconductor R c [Ω]=  [Ωcm]/A[cm 2 ]  c |10 19 cm -3 =5.910 -2 Ωcm 2  c |10 20 cm -3 =6.710 -6 Ωcm 2  c ≈10 -9 Ωcm 2 will be needed Role of concentration

27. Specific Interface Contact Resistance For thermionic emission dominating contact For tunneling mechanism dominating contact Where E 00 is an energy characteristic of the tunneling probability i.e. dominates when E 00 >kT N ≅ 3e19cm -3 Ex.  B ≈0.57eV  c ≈ 10  cm2 27

28. Influence of the Dopant Concentration on Specific Contact Resistance ITRS specifies  c at about 10 -9  cm 2 http://www.itrs.net/links/2012ITRS/Home2 012.htm For  c ≈ 10  8  cm 2 N D ≥10 21 cm -3 28

29. 29 Specific Contact Resistivity Decreases with Doping Levels and Barrier Heights P-type SiN-type Si S. Swirhun, 1987 Barrier heights larger for n- vs p-type

30. Contact Resistance Current crowding Example: R c =10 -8  cm -2 and 0.25x0.25 µm 2 results in 16  30

31. 31

32. 32 Electrical Measurements of Contacts gives overestimation ( R C ) of the contact properties Low resistance KELVIN BRIDGE

33. 33 Historical Development and Basic Concepts Contacts Early structures were simple Al/Si contacts. Highly doped silicon regions are necessary to insure ohmic, low resistance contacts. (2) Tunneling current through a Schottky barrier depends on the width of the barrier and hence N D. In practice, N D, N A > 10 20 cm -3 are required.

34. 34 Scaling: Contacts and Interconnects Global Self - aligned 50% delay from interconnects Earlier:15-20%, then 30- 40% (delay increases with scaling) Contacts between metal/junction using silicides

35. 35 Aluminum Metallization high compressive stress in Al during annealing large All silicides give self-aligned contacts contact area R passive Al contact: SiO 2 native reduced good ohmic! Al 2 O 3 forms, very stable adhesion to Si O 2 Q it during annealing @ 450 0 C H formation High SS of Si in Al0.5% 450 0 C High Si diff in Al SPIKES! in local spots Al - 2-3 µm junctions only! Ti as a sacrificed Barrier TiSi 2 & TiN (=diffusion barrier) Better solution

36. 36 Equilibrium phase diagram of the Si-Al System Spikes Generated In Al Contacts

37. 37 Silicides and Polycides gate contacts local interconnects (require a-Si deposition) SALICIDE PROCESS sputtering T (~ 600 0 C ) C 49 Ti Si 2 - high resistive T ( > 800 0 C ) C 54 Ti Si 2 - low resistive Larger grains Ti also against electromigration

38. 38 Silicides Good adhesion Problems : adhesion stability stress large SILICON CONSUMPTION striped CoSi 2 does not cause problems with resistivity for very narrow lines

39. 39 For 1 nm of metal (Ti, Co, Ni): TiSi 2 - 2.27 nm Si used CoSi 2 - 3.64 nm Si NiSi -1.83 nm Si Bulk Device Critical: Sharp profiles, Small depths Silicide Junction/contact integration: small R s of the contact causes Si consumption thus junction degradation (leakage) Ex. x TiSi2 = 360 - 800 Å R s = 4.5 - 1.7 Ω/sq., Si consumption ≈ x TiSi2, > x CoSi2, <, x NiSi 20-30 nm minimum Short Extension lengths for high transconductance (10 - 20 nm) Shallow Deep junctions for small Drain Induced Barrier Lowering x jdeep ≈70 -50 nm) Surface roughness - due to excess silicidation, phase & structure differences –  must be avoided to limit leakage currents and SB height nonuniformity (ex. small contact sizes).  Flat interfaces for CoSi 2 and NiSi possible

40. 40 Evolution of Silicides in CMOS Main Problems: TiSi2: Sheet resistance oxidation (high T) narrow lines – phase transition, stress, knock on oxygen, surface damage (RIE) leakage (metal diffusion) bridging b/w S/D and G thermal stability – agglomeration TDDB – metal diffusion to G oxide CoSi2: Large Si consumption NiSi Instability at elevated T ~700°C – NiSi 2 = larger Si consumption and higher resistance NiSi is currently used with modifications by: dopant segregation, complementary implantation to adjust Schottky barriers for e - and h +. Iwai, 2002

41. 41 TEM images of 0.1  m TiSi, NiSi, and CoSi lines. Relationship between crystal structure and TiSi line width. TiSi 2 and its Successors Iwai, 2002 CoSi 2 and NiSi scale with line widths

42. 42 TEM images of cross-section of TiSi, NiSi, and CoSi lines. Mechanisms of Silicide Formation and Devices (gates) Iwai, 2002

43. 43 TiSi 2 Salicide Formation Si is the diffuser for CoSi 2 TiSi 2 Creep - up short G - S Less lateral encroachment Consumption of Silicon Large : Ti Si 2 = 138 nm from Ti = 55 nm Si consumed = 125 nm fast diffusion Linear coefficient = fast reaction conductive Growth as in the oxidation process: parabolic and linear

44. 44 Some front-end models have also been applied to back-end processing. Silicide formation is often modeling using the Deal-Grove linear-parabolic model. (7) Simulation of TiSi 2 formation using FLOOPS [11.32] on a 0.35  m wide gate structure. Left: before formation anneal step. Right: after formation anneal step: 30 sec at 650˚C in a nitrogen atmosphere TiSi 2 Salicide Formation

45. 45 Silicide Formation and Scaling of Devices 650 0 C/ 30 ” Ar @ the top of the oxide spacer TiN growth: 20% of TiSi 2 parameters 32.5 nm Ti 44 nm Si 50 nm TiSi 2 + 27 nm TiN Not all Ti consumed See Deal & Grove Linear / Parabolic growth Anneal now in N 2 2µm wide channel 0.35µm wide channel 48 nm TiSi 2 from 43 nm Si

46. 46

47. 47 Iwai, 2011 Kittl et al., 2008 PMOS – challenge - P+ (100) Si, 310°C RTP

48. 48 NiSi 2 technology suppresses leakage current: Flat interface and no Si consumption No defects in the Si substrate Iwai, 2011 Flat NiSi interface - from a NiSi 2 Source

49. 49 Chang Y. Kang, Sematech Symp., Korea 2011

50. 50 Chang Y. Kang, Sematech Symp., Korea 2011

51. 51 Contacts Optimization Interface Engineering to reduce Schottky Barrier Height Co-implantation (dopants Sb, As, B or other elements ex.for S  B ~0.5 eV, Al ~0.4eV, and Nitrogen) Dipole Engineering Ni-Alloys (for Si – silicides and for SiGe/Ge – germanides) Raised (diffused) S/D show superior properties Ioff/Ion than Schottky S/D – in FinFETs (discussed later). Chang Y. Kang, Sematech Symp., Korea 2011 Hobbs; Jammy, Sematech Symp., Taiwan,2010 Sb NiPtSi + charged Sb at the interface

52. 52 Implantation was done prior to silicidation Yuri Erokhin, IWJT, 2012 SBH modification by PAI and Selected co- Implantation Steps

53. 53 THE FUTURE OF BACKEND TECHNOLOGY Contacts will be now connected to interconnects – more challenges! Reduce metal resistivity - use Cu instead of Al. Aspect ratio - advanced deposition, etching and planarization methods. Reduce dielectric constant - use low-K materials.