1. CMOS DYNAMIC LOGIC DESIGN
Integrated Circuits
Spring 2001
Dept. of ECE
University of Seoul

2. Dynamic Logic Motivation
 Complementary CMOS Logic
  VOH=VDD, VOL=GND
  No Static Power Dissipation
  For Fan-In of N, (2N) Transistors Required
  Series Network Unavoidable
 pseudo-nMOS Logic
  For Fan-In of N, (N+1) Transistors Required
  Series Network Avoidable
  VOLGND
  Static Power Dissipation
 Dynamic Logic
 Combination of Two Design Approaches

3. Basic Principle – fn Network
 CLK=L [PRECHARGE]
 MN OFF : Y can’t go down to GND
 MP ON : Y prechaged to VDD
 CLK=H [EVALUATION]
 MP OFF
 MN ON
Y can go down to GND or
stay at VDD
according to PDN evaluation.
PDN

4. Basic Principle – fp Network
 CLK=L [PRECHARGE]
 MP OFF : Y can’t go up to VDD
 MN ON : Y prechaged to GND
 CLK=H [EVALUATION]
 MN OFF
 MP ON
Y can go up to VDD or
stay at GND
according to PUN evaluation.
PUN

5. fn Network – Operation
PRECHARGE
EVALUATION

6. fn Network – Characteristics
 Logic – PDN consists of nMOS Transistors
 Number of Transistors: N+2 
 Faster Switching Speed due to Reduced # of Transistors
 Ratioless Logic: VOH=VDD, VOL=GND 
 No Static Power Dissipation, Only Dynamic Power Dissipation 
 Reduced Noise Margin (NML) 
VIL, VIH & VM

7. fn Network – Example  4-Input NAND  Waveform tpHL  How about tpLH?

8. fn Network Problem – Leakage Current
 ILK = IRD (Reverse-Biased Diode) + IWI (Weak-Inversion) 
 For Proper Logic Operation, VDD-DVLK > VIH

9. Leakage Current Example
 ILK= 10nA (for example)
 CL= 32.75fF (pp. 133 in textbook)
 Leakage Ripple
 High Y
 VIH for Inverter
VIH=2.92V (pp. 128 in textbook)

10. fn Network Problem – Charge Sharing
 Before A Rising,
 After A Rising,
 Charge Sharing Ripple

11. Solution - Charge Sharing Problem

12. fn Network Problem – Clock Feedthrough
might forward-bias PN junction

13. fn Network Problem – Cascading
 Ideally, Y = NOT(X) = NOT(NOT(A)) = A = “H”
 Non-Zero Falling X-node  Y-node Also Falling
until X-node reaches VTHN
Basic Problems: Outputs Precharged to VDD & They drives nMOSFET.

14. DOMINO Logic  Solve Problem of Cascading
 But Still Dynamic Logic  Leakage, Charge Sharing, Clock Feedthrough
 Can’t Make Inverting Logic such as NAND, NOR, …
 Very High Speed Operation Achievable

15. ZIPPER Logic  Precharged to VDD (GND)  Drives pMOS (nMOS) Logic
 Speed Unbalance between PDN (nMOS) & PUN (pMOS)
 Higher Speed Than Domino Due to Lack of Inter-stage Inverters
 DEC Alpha Processor

16. CMOS Logic Comparison