1. Szu-Wei Huang, C-V Lab, GIEE of NTU 1 黃 思 維 F90943078 Graduate Institute of Electronics Engineering National Taiwan University Advanced Multi-Gate Technologies for the Sub-25 nm Regime

2. Szu-Wei Huang, C-V Lab, GIEE of NTU 2 Conventional Planar Bulk MOSFET Challenges for Planar Bulk MOSFETs Scaling Gate Leakage Current Packing Density Drive Current Short Channel Effect (SCE) Drain Induced Barrier Lowing (DIBL) Device Scalability Process Complexity

3. Szu-Wei Huang, C-V Lab, GIEE of NTU 3 Advantages of Non-Planar MOSFET Ultra-Thin Body (UTB) Structure Current Driven by Multi-Gate Excellent Short-Channel Behavior Better Gate-to-Channel Controllability Reduced DIBL Potential Scalability CMOS-compatible Process

4. Szu-Wei Huang, C-V Lab, GIEE of NTU 4 Non-Planar MOSFET  Device Evolution of Non-Planar MOSFETs  Dimension Restriction of Non-Planar MOSFETs

5. Szu-Wei Huang, C-V Lab, GIEE of NTU 5 Thickness of Si Body T sb UTB-SOI DST FinFET  -FET     T sb ≤ 1/3 L g T sb ≤ 2/3 L g T sb ≤ L g

6. Szu-Wei Huang, C-V Lab, GIEE of NTU 6 FinFET with 10-nm Gate Length Layout and Process Flow  Fabricated with (110) Orientation to Enhance Hole Mobility

7. Szu-Wei Huang, C-V Lab, GIEE of NTU 7 FinFET with 10-nm Gate Length Cross-section and Top View T ox = 17 Å T sb : 17~26 nm Double Gate Device

8. Szu-Wei Huang, C-V Lab, GIEE of NTU 8 FinFET with 10-nm Gate Length Electrical Characteristics W CH = 2  H fin SCE Reduced Due to : Thicker T sb Dual Gate Structure Abrupt S/D Junction

9. Szu-Wei Huang, C-V Lab, GIEE of NTU 9 FinFET with 10-nm Gate Length Carrier Mobility on (110) Orientation Field in Inversion Layer  (110) Crystal Orientation Hole Mobility 

10. Szu-Wei Huang, C-V Lab, GIEE of NTU 10 FinFET with 10-nm Gate Length CMOS-FinFET Inverter

11. Szu-Wei Huang, C-V Lab, GIEE of NTU 11 FinFET with 10-nm Gate Length Device Performance Double Gate NMOSPMOS L g (nm)10 T sb (nm)17~26 V DD (V)1.2 T ox (Å)17 I d ( µA/µm ) 446356 Swing (mV/dec)125101 DIBL (mV/V)71120 Gate Delay (ps)0.340.43

12. Szu-Wei Huang, C-V Lab, GIEE of NTU 12  -FET with 25-nm Gate Length Triple-Gate Device Structure Gate Extension Under Si Body Decreasing Drain-Induced-Barrier-Lowing Increasing Gate-to-Channel Controllability

13. Szu-Wei Huang, C-V Lab, GIEE of NTU 13  -FET with 25-nm Gate Length Cross-Section View T ox = 17~19 Å T sb = 25 nm H Si = 55 nm T sb  Shielding Electrical Field from Drain Reducing Parasitic Resistance

14. Szu-Wei Huang, C-V Lab, GIEE of NTU 14 Characteristics of |V D |=1V Version  -FET with 25-nm Gate Length W CH = 2  H fin + T sb

15. Szu-Wei Huang, C-V Lab, GIEE of NTU 15  -FET with 25-nm Gate Length Characteristics of |V D |=0.7V Version Gate Delay (ps) NMOS0.39 PMOS0.88 W CH = H fin

16. Szu-Wei Huang, C-V Lab, GIEE of NTU 16  -FET with 25-nm Gate Length Gate Delay Comparison of |V D |=0.7V Version Gate Delay is Defined as ( CV/I )

17. Szu-Wei Huang, C-V Lab, GIEE of NTU 17  -FET with 25-nm Gate Length Demonstration of Multiple CMOS  -FET Circuit

18. Szu-Wei Huang, C-V Lab, GIEE of NTU 18 Comparison of Device Geometry HW UTB-SOI≤1/3L g  FinFET  ≤2/3L g  -FET ≥2 L g LgLg If Channel Length = L g

19. Szu-Wei Huang, C-V Lab, GIEE of NTU 19 Process Refinements of FinFET Hydrogen Annealing  Higher Surface Quality  Improved Drive Current  Lower Gate Noise Metal Gate Engineering  Ideal Mobility  Lower Gate Leakage Current  Higher Transconductance  Competitive I ON /I OFF Ratio  Adjustable V t

20. Szu-Wei Huang, C-V Lab, GIEE of NTU 20 Hydrogen Annealing Increased Surface Si Migration Rate Red Circle: Improved Line Edge Roughness Blue Circle: Improved Sidewall Roughness

21. Szu-Wei Huang, C-V Lab, GIEE of NTU 21 Hydrogen Annealing  Increased Current Due To Decreased Surface Trap Density  NMOS Drive Current is More Degraded Due To the Closer Inversion Charge Centroid of Electrons

22. Szu-Wei Huang, C-V Lab, GIEE of NTU 22 Hydrogen Annealing Equivalent Gate Voltage Noise S VG S VG =Output Drain Current Noise/Transconductance Hydrogen Annealing Forms High Quality Surface

23. Szu-Wei Huang, C-V Lab, GIEE of NTU 23 Hydrogen Annealing Carrier Mobility on the (110) Orientation Mobility Degradation Due to Surface Roughness Scattering µ SR  1/(E eff Δ) 2, where Δ is the Root- Mean-Square Value of Surface Roughness

24. Szu-Wei Huang, C-V Lab, GIEE of NTU 24 Metal Gate Engineering Gate Work Function for FDSOI CMOS FinFET Technology is 4.4-5.0 eV. Molybdenum Gate  A work Function of ~5V which is suitable for p-FinFET  Nitrogen Implanted into Molybdenum Followed by Annealing Results in Work Function of ~4.4V which is suitable for n-FinFET Molybdenum-Gated FinFET

25. Szu-Wei Huang, C-V Lab, GIEE of NTU 25 Metal Gate Engineering Molybdenum-Gated FinFET Nitrogen was implanted at a tilt of 60 O Poly-Silicon was used to prevent oxidation and ion channeling

26. Szu-Wei Huang, C-V Lab, GIEE of NTU 26 Metal Gate Engineering Molybdenum-Gated FinFET  Mo Gate was etched by Cl 2 and O 2 plasma  40 nm Mo Gate with 400 nm cap Poly-Si

27. Szu-Wei Huang, C-V Lab, GIEE of NTU 27 Metal Gate Engineering Molybdenum-Gated FinFET PVD Mo is discontinuous due to the undercut of buried oxide caused by over-etching by HF

28. Szu-Wei Huang, C-V Lab, GIEE of NTU 28 Metal Gate Engineering Molybdenum-Gated FinFET Multi-V t is observed by nitrogen implantation Gate work Function was changed by nitrogen implantation

29. Szu-Wei Huang, C-V Lab, GIEE of NTU 29 Metal Gate Engineering NiSi-Gated FinFET (110) Orientation NiSi Gate CoSi 2 Raised S/D L g = 100 nm T sb = 25 nm T ox = 16 Å

30. Szu-Wei Huang, C-V Lab, GIEE of NTU 30 Metal Gate Engineering NiSi-Gated FinFET W = 2  H fin

31. Szu-Wei Huang, C-V Lab, GIEE of NTU 31 Metal Gate Engineering NiSi-Gated FinFET 10% Gm Gain achieved by the elimination of Poly-Depletion Effect

32. Szu-Wei Huang, C-V Lab, GIEE of NTU 32 Metal Gate Engineering NiSi-Gated FinFET Gate Leakage of NiSi-Gated FinFET is Lower than Poly-Si-Gated FinFET

33. Szu-Wei Huang, C-V Lab, GIEE of NTU 33 Conclusion 10 nm CMOS FinFET and 25 nm CMOS  -FET have been successfully fabricated. Excellent SCE and DIBL and other electrical characteristics of both FinFET and  -FET are obtained. CMOS circuit for both 10 nm CMOS FinFET and 25 nm CMOS  -FET are demonstrated. Hydrogen annealing has verified to smoothen the line edge and sidewall surface roughness, in which the mobility and the gate noise are therefore improved. The gate work function has shown to be adjusted by using the metal/silicide gate to acquire desired device properties.

34. Szu-Wei Huang, C-V Lab, GIEE of NTU 34 References [1] J. Kedzierski, et al, “Metal-gate FinFET and fully- depleted SOI devices using total gate silicidation,” IEDM Tech. Dig., 2002, pp. 247-250. [2] B. Yu, et al, “FinFET Scaling to 10 nm Gate Length,” IEDM Tech. Dig., 2002, pp. 251-254. [3] F.-L. Yang, et al, “25 nm CMOS Omega FETs,” IEDM Tech. Dig., 2002, pp. 255-258. [4] Y.-K. Choi, et al, “FinFET Process Refinements for Improved Mobility and Gate Work Function Engineering,” IEDM Tech. Dig., 2002, pp. 259-262.