1. 1 1 JEITA STD-TSC updates JEITA EDA standardization subcommittee, Vice chair IEC TC93 WG2, Co-convener NEC System Technologies Satoshi Kojima IEEE-DASC meeting at EDSFair2010, Yokohama 9:30 -11:00, 29 rd January 20010 (JST) CM4 room at Pacifico Yokohama JEITA EDA standardization subcommittee, Chair OKI Semiconductor Ichiro Yamamoto

2. 2 Copyright(C) JEITA 2008 IEEE-DASC Yokohama meeting, 29Jan2010© Copyright 2010 JEITA Introduction  Organization chart and updates of STD-TSC Some concerns on DASC activities  Design language harmonization  BVDL: the Bird’s-eye View for Design Languages Summary Summary - Outline -

3. 3 Copyright(C) JEITA 2008 IEEE-DASC Yokohama meeting, 29Jan2010© Copyright 2010 JEITA JEITA Structure and Management Japan Electronics and Information Technology Industries Association JEITA Policy and Strategy Board Environment Board Consumer Electronics Board IT and Industrial Systems Board Display Devices Board Electronic Components Board Semiconductor Board (JEITA-JSIA) Semiconductor Industrial Affairs Committee Semiconductor International Affairs Committee Semiconductor Technology Committee Marketing Committee Road Map Committee EDA Technical Committee (EDA-TC) - Member : 16 Companies Fujitsu ML, Panasonic, NEC EL, Toshiba, Renesas, Rohm, Sanyo, Sharp, Sony, Seiko Epson, Synopsys, JEDAT, Mentor, Ricoh, Toppan, Zuken Elmic

4. 4 Copyright(C) JEITA 2008 IEEE-DASC Yokohama meeting, 29Jan2010© Copyright 2010 JEITA EDA-TC Structure in fiscal year 2009 EDA Technical Committee EDA Standardization Technical Sub-Committee SystemC Working Group NPD (Nano-scale Physical Design) Working Group EDSFair 2010 Executive Committee Acceleration of Standardization Solution for Technical Challenges Promotion of EDA Technology Chair: Ohta (Panasonic) Chair : Saito (SONY) Chair: T.Kanamoto (Renesas) Chair : Yamamoto (OKI Semicon), Vice-chair : Aono (EPSON) Kojima (NECST) Chair : Imai (Toshiba) Power Format Working Group Chair : T.Nakamori (Fujitsu ML)

5. 5 Copyright(C) JEITA 2008 IEEE-DASC Yokohama meeting, 29Jan2010© Copyright 2010 JEITA Members: semiconductor vendors, EDA vendors and academia  Chair: Yamamoto (OKI Semicon)  Vice-chairs: Aono (EPSON), Kojima (NECST) To reflect opinions on technical and business issues as a group of EDA power users to De Jure standard bodies such as IEEE and IEC TC93 To raise issues on design flows to solve today and future design challenges from the member companies and to propose what standards can contribute to solve them Two subsidiaries are actively working on  SystemC Working Group  Power Format Working Group EDA Standardization TSC Activities

6. 6 Copyright(C) JEITA 2008 IEEE-DASC Yokohama meeting, 29Jan2010© Copyright 2010 JEITA Yamamoto-san took leadership to finalize BVDL: the Bird’s- eye View for Design Languages and shared with members of IEC TC93 at Kyoto meeting in late September, 2009. Now working on Fiscal Year 2010 plans  The chair might succeed to Imai-san in Toshiba from Yamamoto-san.  Power Format WG might make a pause since they accomplished the goal.  A new WG will be formed and aim to harmonize co-design environment among LSI, Package and Board. Fukuba-san in Toshiba and his team have been intensively making preparation. EDA Standardization TSC Activities (Cont’d)

7. 7 Copyright(C) JEITA 2008 IEEE-DASC Yokohama meeting, 29Jan2010© Copyright 2010 JEITA Collaboration w/IEEE and IEC Domestic collaboration  To dispatch a chair and some experts to WG2 of IEC TC93 JNC in IEICE (The Institute of Electronics, Information and Communication Engineers) and to lead the activities of the WG2 JNC Global collaboration  Worked with P1800WG (SystemVerilog), P1666WG (SystemC) and P1801WG (Power format) in IEEE-DASC, reviewing the drafts and participating in the balloting. Planning work with P1481(SSPEF)  Has been a member of IEEE-SA since 2004 and participated in balloting such as IEEE1800, IEEE1666 in 2005 and IEEE1801 in 2008  Kojima has been a JEITA DR of IEEE DASC since 2008  Kojima has been a Co-convener of TC93 WG2 since 2000 and worked with Dennis Brophy in USNC  IEEE-IEC Dual Logo agreement made in 2003 accelerates EDA global standardization such as SytemC, System Verilog…

8. 8 Copyright(C) JEITA 2008 IEEE-DASC Yokohama meeting, 29Jan2010© Copyright 2010 JEITA IEICE TC93 JNC JEITA EDA STD-TSC WG2 JNC IEEE IEEE-SA IEC TC93 Int’l WG2 Accellera, OSCI WG2 JNC EDA-TC WGs (P1666, P1801, P1481, …) DASC CAG NesCom, RevCom SC-WG PF-WG NPD-WG Membership Hand-offs Collaboration Collaboration scheme Dual Logo agreement Representatives

9. 9 Copyright(C) JEITA 2008 IEEE-DASC Yokohama meeting, 29Jan2010© Copyright 2010 JEITA EDA standards provide a mechanism for defining common semantics for integrated design systems among various tools To define common SoC design flow and then categorize existing standards and emerging ones To set strategies of EDA standardization activities for every category JEITA to set strategies of EDA standards System Design Specification (Function + Constraints) Analyze Implement w/Opt. Equivalence check Circuit Logic Software Scan/BIST Place Route DFM DFT Noise Power Timing Area Communicate Libraries Verification Data for manufacturing Testability Performance Function

10. 10 Copyright(C) JEITA 2008 IEEE-DASC Yokohama meeting, 29Jan2010© Copyright 2010 JEITA Design languages harmonization JEITA had some good lessons-learned through power format standardization activities under 2 formats issues of UPF and CPF  Criteria to qualify De Jure standard is applicable for practical SoC design flow or not  Unification is best, but in reality interoperability and harmonization are indispensable An AMS language is derived from a digital design language to cover digital- analog mixed signal world. In result, there are three AMS languages in an EDA community  VHDL-AMS is IEEE standard and might be in an academia  Verilog-AMS might be De Facto standard in the market  SystemC-AMS will be OSCI standard soon

11. 11 Copyright(C) JEITA 2008 IEEE-DASC Yokohama meeting, 29Jan2010© Copyright 2010 JEITA Bird’s-eye view for Design Languages BVDL aims to make full use of planning and decision-making on JEITA activities and to facilitate global understanding of various design languages, classified into De Jure standards, Forum standards and De Facto standards BVDL is a set of charts to show the position that each design language occupied in the design technology along a generally accepted design flow  The X-axis shows design phases of the flow  The Y-axis shows design objects which is a set of design data such as hardware description, verification description, design constraints and so on

12. 12 Copyright(C) JEITA 2008 IEEE-DASC Yokohama meeting, 29Jan2010© Copyright 2010 JEITA Summary To update JEITA standardization activities such as STD-TSC, SystemC WG, and Nano-scale physical design WG To talk about some concerns on DASC activities Design languages harmonization BVDL introduction

13. 13 JEITA : Japan Electronics and Information Technology Industries Association ( URL http://www.jeita.or.jp) EDA-TC : EDA Technical Committee ( URL http://eda.ics.es.osaka-u.ac.jp/jeita/eda/index.html)

14. 14 Nano-scale Physical Design Working Group Activities  Pick out the problems on physical design and verification of LSI in the next generation technology node.  Make design rules and guidelines which specifies the library exchanged between a semiconductor vendor and its customer, design information, etc.  Standardize libraries, which improve accuracy, compatibility, and efficiency of physical design and verification.  Build benchmarking data set, which test accuracy of library verification.

15. 15 Nano-scale Physical Design Working Group Activities related to P1481-SSPEF  Concentrating on looking at the linear sensitivity model defined in SSPEF, to specify suitable range of the global process variability in upcoming 22nm era. Interconnect cross-section ⊿w⊿w⊿w⊿w C