1. Institute of Applied Microelectronics and Computer Engineering College of Computer Science and Electrical Engineering, University of Rostock Slide 1 Spezielle Anwendungen des VLSI – Entwurfs Applied VLSI design Layout for ASIC netlist Results of Phase 4 Michael Rethfeldt

2. Institute of Applied Microelectronics and Computer Engineering College of Computer Science and Electrical Engineering, University of Rostock Slide 2 ASIC netlist set target_library [concat $CORESVTtyp10V $COREHVTtyp10V $CORELVTtyp10V] set_operating_conditions nom_1.00V_25C set frequency 110 (was 100) set_max_leakage_power 100 nW ungroup -all -flatten -simple_names compile_ultra -area_high_effort_script

3. Institute of Applied Microelectronics and Computer Engineering College of Computer Science and Electrical Engineering, University of Rostock Slide 3 ASIC layout – positive effects Core utilization - freq. best around 90 % - below  long wires to core sides, slower - above  limited routing possibilities, slower Core aspect ratio - IO pads left & right  H > W (0.9:1, 1.5:1, 2:1, 3:1, 4:1, 5:1) Antenna fixing - turned off in nano-route  slight speed increase

4. Institute of Applied Microelectronics and Computer Engineering College of Computer Science and Electrical Engineering, University of Rostock Slide 4 ASIC layout – negative effects Limited metal usage - limited to layer 4 (5 used before) - speed decrease Post route optimizations - timing only - leakage only - leakage & timing  always high leakage increase Gate libraries - use only high Vt instead of mixed Vt  -2nW leakage, speed decrease  worse metric Power stripes  speed decrease (place & route limitation)

5. Institute of Applied Microelectronics and Computer Engineering College of Computer Science and Electrical Engineering, University of Rostock Slide 5 ASIC layout – misc. Power ring dimensions - tried 2µm, 5µm, 10µm width  no effects on speed / leakage for used design

6. Institute of Applied Microelectronics and Computer Engineering College of Computer Science and Electrical Engineering, University of Rostock Slide 6 Final ASIC layout with pads  leakage > 12 mW !!

7. Institute of Applied Microelectronics and Computer Engineering College of Computer Science and Electrical Engineering, University of Rostock Slide 7 Metric ASIC netlist phase 3 Total cell area A23892 Frequency f100 MHz Number of cycles N cycles 41375 Operation time t OP 0.41375 ms Average error E avg 0.249947 Cell leakage power P leak 101.9216 nW Metric6.58488243 * 10 -13 Ws

8. Institute of Applied Microelectronics and Computer Engineering College of Computer Science and Electrical Engineering, University of Rostock Slide 8 Metric ASIC layout phase 4 Timing (T min / f max )12.867 ns / 77.718193 MHz Power (P dyn / P leak )205.5079 µW / 102.3966 nW N cycles / Operation time t OP 41375 / 0.532372125 ms Average error E avg 0.249947 Core size119.44 x 305.8 µm² Core utilization90.00 % Metric8.512255087 * 10 -13 Ws