1. Computer Engineering 1502 Advanced Digital Design Professor Donald Chiarulli Computer Science Dept. don@cs.pitt.edu

2. Course Assistants and Resources Sam Dickerson –TA Office – 271-I Benedum Hall sdickerson@ee.pitt.edu Joe Jezak-TA Office – 5426 Sennott Square jjezak@cs.pitt.edu

3. Goals of this course  Learn tools and techniques of modern digital design for large scale digital systems  Complement your Computer Architecture Course (CoE 1541) with actual design experience for the processor covered in that course.  PREREQUISITE – CoE 0501  CO-REQUISITE – CoE 1541 Pre/Co requisites are non-negotiable

4. Things to do today 1.Set up your account, make sure the tools work properly 2.Proceed with the tools tutorial, make sure that you do the library setup part. 3.Work on unit 1a up to (but not including “adding subblocks to block diagram”). After the presentation

5. What’s expected of you Most of the work in this class is divided into a series of Project that will be combined into your first full processor design Each project will begin with a lecture (approx 1 hour) at the beginning of class You will have one to three weeks to complete the unit depending on the complexity Units will be checked individually by myself or the TA -- demonstrations are required to receive credit for a unit Units not checked on the due date will be considered late with credit deducted Units more than one week late will receive no credit (but you will still have to do them)

6. Projects, Schedule and Grading* Credit Project 1 - Self Directed Tutorial Learn Mentor Tools Completed individually 2 weeks10% Project 2 - A Simple State Machine: UART Controller 1 st Design/State Machine Groups of 2 3 weeks15% Project 3 - 32-bit Pipelined MIPS CPU 5 stage, pipelined RISC processor Groups of 2 4 weeks15% Project 4 - The System Bus Interface: Wishbone Connect to standard System Bus Add memory controller and L1 Cache Groups of 2 3 weeks15% Project 5 – Exception Handling Add support for multiple Interrupt and Exception states Groups of 2 3 weeks15% Practical Exam (Final)30% * Exact percentages are subject to adjustment if necessary

7. Final Exam This is a design class, the final exam will test how effectively you have learned to tools and techniques of digital design You will be given the specification for a small device that you should be familiar with either from experiences in this or other classes You will be given two hours to implement this device using the software tools you have used in the course Grading will be based on completeness, functionality and quality of the design that you produce Since this is “almost” the only individual grade you will receive in this class, it will weigh heavily in the computation of your course grade

8. Software Tools HDL Designer Suite - Mentor Graphics Inc FGPA Advantage - Design Entry Tool ModelSim - Simulator Quartus - Design Synthesis FPGA place and Route tools

9. Design Flow FPGA Advantage VHDL Place and Route FPGA Hardware ModelSim Design EntryVerification Quartus Logic Synthesis Logic Analyzer

10. Hardware platform: Field Programmable Gate Arrays Altera Cyclone II 512KB SRAM 8MB SDRAM 56 Bits bit-level I/0 (switches/buttons/L EDs) 8 7-segment LED serial I/O and more…. Altera DE2 Development board

11. FPGA Structure

12. Where to Start www.cs.pitt.edu/~don/coe1502

13. Introduction to Design Tools COE 1502

14. Review: Tools, functions, design flow Four tools we will use in this course – HDL Designer Suite FPGA Advantage – IDE to create hierarchical designs and generate HDL ModelSim – Robust logic simulator Synthess (Quartus) – Synthesizes HDL into gate-level netlists using device cell libraries

15. Review: Tools, functions, design flow VHDL code Generate Proprietary binary format Compile Simulate using ModelSim Load onto FPGA and test using LA FPGA Advantage Create symbolic designs Proprietary text format SynthesizePlace and Route Quartus Design Flow

16. Libraries in FPGA Advantage A library is a collection of components – Components have one or more views (implementations) Block diagram, truth table, flow chart, state machine, VHDL architecture – Each view has representations: Graphics, VHDL, simulator netlist, synthesis netlist CPUcontrol_unit CPU_lib VHDL archstate diagram gen. VHDLsim. binarysynth. netlist library component view representation graphics block diagram 2block diagram 1 ALU

17. Components Library components can be instantiated in other designs – Shown as green blocks Exportable to other designs – Libraries also contain “blocks” Attached to the design they were created in Shown as blue blocks – Embedded blocks – embedded code local block diagram Shown as yellow blocks Embeds behavior into structure

18. Libraries in FPGA Advantage Libraries are stored in four subdirectories in your group directory (e.g. I:\alpha) – For each library you use or create, library mappings to these directories must be specified – The mappings for your set of libraries are stored in your project file Lives in your group directory I:\alpha \ALU_lib \CPU_lib \hds \hdl \work \ls source directory HDL directory simulation directory synthesis directory

19. Projects A project in FPGA Advantage is a set of library mappings Create a new project in your user workspace – “tutorial”

20. Projects, Libraries, Components, Views tutorial ALU_Lib ALU Src (hds) (graphical view) HDL (generated) Downstream (compiled for sim) Downstream (compiled for synth) Project Library Component

21. Example Design: ALU Open HDL Designer and create your project

22. Example Design: ALU Library and project views in Design Manager…

23. Example Design: ALU

24. Example design: ALU Specifications for ALU – GOAL: implement all logical, arithmetic, shift, and comparison operations in MIPS instruction set Operations – Bit-wise AND, OR, XOR, and NOR – Signed and unsigned addition, subtraction Overflow detection, zero-result detection – Signed and unsigned set-on-less-than comparison – Logical shift left and right, arithmetic shift right – Must accept 2 x 32-bit operands and produce a 32-bit result

25. Example design: ALU Inputs – A, B (32 bits) – SHAMT (how many bits?) – ALUOP (how many bits?) 13 total operations Outputs – C (32 bits) – Overflow – Zero

26. Example design: ALU We will work top-down to design the ALU – First step is to create top-level design – Need to choose a view which will implement a VHDL architecture – View type: block diagram Implements structural VHDL – From design browser… File | New | Graphical View | Block Diagram

27. Example Design: ALU

28. Example design: ALU First, let’s discuss the block diagram toolbars… One level up/Save Add block/component Add embedded block Add signal/bus Add ports Generate VHDL and simulate

29. Example design: ALU First, add interface signals with ports (using the toolbar tool, “wire with port”)… Note signal widths (in wire properties)

30. Example design: ALU Save the block diagram into the ALU library – The component name will be “ALU” Let’s look at the ALU symbol… – Click “up” in BD, or – Use the design browser Source file Symbol file

31. Example design: ALU The symbol looks something like this… – We can change the shape and pin locations here Right click, then “Autoshapes” Make the symbol look like an ALU symbol

32. Example design: ALU Go back to the block diagram window and let’s generate VHDL for our design… Next, let’s take a look at the VHDL that we generated…

33. Example design: ALU -- VHDL Entity ALU.ALU.symbol -- -- Created: -- by - ajnoyola.UNKNOWN (TWEETY) -- at - 23:46:41 03/10/2006 -- -- Generated by Mentor Graphics' HDL Designer(TM) 2005.1 (Build 83) -- LIBRARY ieee; USE ieee.std_logic_1164.all; USE ieee.std_logic_arith.all; ENTITY ALU IS PORT( A : IN std_logic_vector (63 DOWNTO 0); ALUOp : IN std_logic_vector (3 DOWNTO 0); B : IN std_logic_vector (63 DOWNTO 0); SHAMT : IN std_logic_vector (4 DOWNTO 0); SHAMT_HIGH : IN std_logic; Overflow : OUT std_logic; R : OUT std_logic_vector (63 DOWNTO 0); Zero : OUT std_logic ); -- Declarations END ALU ; -- -- VHDL Architecture ALU.ALU.struct -- -- Created: -- by - ajnoyola.UNKNOWN (TWEETY) -- at - 23:46:42 03/10/2006 -- -- Generated by Mentor Graphics' HDL Designer(TM) 2005.1 (Build 83) -- LIBRARY ieee; USE ieee.std_logic_1164.all; USE ieee.std_logic_arith.all; ARCHITECTURE struct OF ALU IS -- Architecture declarations -- Internal signal declarations BEGIN -- Instance port mappings. END struct;