1. Eng. Mohammed Timraz Electronics & Communication Engineer University of Palestine Faculty of Engineering and Urban planning Software Engineering Department Digital Logic Design ESGD2201 Wednesday, 18 th November 2009 Lecture 11 Function of Combinational Logic.

2. 1. Basic Adders. 2. Parallel Binary Adders. 3. Comparators. 4. Decoders. 5. Encoders. 6. Code Converters. 7. Multiplexers. 8. Demultiplexers. Agenda Function of Combinational Logic.

3. Basic Adders:  Adders are important not only in computers, but in many types of digital systems in which numerical data are processed.  An understanding of the basic adder operation is fundamental to the study of digital systems. Function of Combinational Logic.

4. 1. The Half Adder: Recall the basic rules for binary addition. Function of Combinational Logic. These operations are performed by a logic circuit called a half-adder. A+BSumCarrier 0+000 0+110 1+010 1+101

5. 1. The Half Adder: Half Adder Logic Symbol: The half-adder accepts two binary digits on its inputs and produces two binary digits on its outputs, a sum bit and a carry bit. Function of Combinational Logic. Logic symbol for a half-adder.

6. 1. The Half Adder: The Half Adder Truth Table: Function of Combinational Logic. ∑=sum C out = output carry A and B = input variables (operands)

7. 1. The Half Adder: Function of Combinational Logic. From the logical operation of the half-adder as stated in the truth Table, expressions can be derived for the sum and the output carry as functions of the inputs. Notice that the output carry ( C out) is a 1, only when both A and B are 1s; therefore, (Cout) can be expressed as the AND of the input variables. Now observe that the sum output (∑) is a 1 only if the input variables, A and B, are not equal. The sum can therefore be expressed as the exclusive-OR of the input variables. 1 2

8. 1. The Half Adder: The Half Adder Logic Diagram Function of Combinational Logic. From Equations (1) and (2), the logic implementation required for the half- adder function can be developed. The output carry is produced with an AND gate with A and B on the inputs, and the sum output is generated with an exclusive-OR gate, as shown in the following Figure. The Half Adder Logic Diagram

9. 2. The Full Adder: The second basic category of adder is the Full-adder. Function of Combinational Logic. The basic difference between a full-adder and a half-adder is that: 1- The full-adder accepts an input carry. 2- A logic symbol for a full-adder as shown in the following Figure. 3- The truth table in the following Table shows the operation of a full-adder.

10. The Full Adder: Half Adder Logic Symbol Function of Combinational Logic. Logic symbol for a Full-adder. The full-adder accepts three inputs including an input carry and generates a sum output and an output carry.

11. The Full Adder: The Full Adder Truth Table Function of Combinational Logic. C in = input carry, sometimes designated as CI C out = output carry, sometimes designated as CO ∑=sum A and B = input variables (operands)

12. The Full Adder: Function of Combinational Logic.  The full-adder must add the two input bits and the input carry.  From the half-adder we know that the sum of the input bits A and B is the exclusive-OR of those two variables,.  For the input carry (C) to be added to the input bits, it must be exclusive-OR with, yielding the equation for the sum output of the full-adder.

13. The Full Adder: The Full Adder Logic Diagram Function of Combinational Logic. (a) Logic required to form the sum of three bits  This means that to implement the full-adder sum function: Two exclusive-OR gates can be used. The first must generate the term, The second has as its inputs the output of the first XOR gate and the input carry, as illustrated in the following Figure.

14. The Full Adder: The Full Adder Logic Diagram Function of Combinational Logic. (b) Complete logic circuit for a full-adder (each half-adder is enclosed by a shaded area)

15. The Full Adder: The Full Adder Logic: Function of Combinational Logic.  The output carry is a 1 when both inputs to the first XOR gate are 1s or when both inputs to the second XOR gate are 1s.  The output carry of the full-adder is therefore produced by the inputs A ANDed with B and AND with C in.  These two terms are ORed, as expressed in the following Equation.  This function is implemented and combined with the sum logic to form a complete full-adder circuit, as shown in the Figure (b).

16. The Full Adder: The Full Adder Logic Diagram Function of Combinational Logic. (b) Complete logic circuit for a full-adder (each half-adder is enclosed by a shaded area)

17. The Full Adder: The Full Adder Implemented with half adder Logic: Function of Combinational Logic. Notice in Figure (b) there are two half-adders, connected as shown in the block diagram of the following Figure (a), with their output carries OR. (a) Arrangement of two half-adders to form a full-adder

18. The Full Adder: The Full Adder Logic Symbol: Function of Combinational Logic. The logic symbol shown in the following Figure (b) will normally be used to represent the full-adder. (b) Full-adder logic symbol

19. Example 1: Determine an alternative method for implementing the full-adder. Function of Combinational Logic. Solution: Referring to the truth Table of full adder, you can write sum-of-products expressions for both ∑ and C out by observing the input conditions that make them 1s. The expressions are as follows: C in = input carry, C out = output carry, ∑=sum A and B = input variables (operands)

20. Example 1: Determine an alternative method for implementing the full-adder. Function of Combinational Logic. Solution: Referring to the truth Table of full adder, you can write sum-of-products expressions for both ∑ and C out by observing the input conditions that make them 1s. The expressions are as follows:

21. Example 2: Function of Combinational Logic. Mapping the two expressions of the full adder on the Karnaugh map.

22. Solution: Function of Combinational Logic. Mapping these two expressions on the Karnaugh maps in the following Figure, you find that the sum (∑) expression can’t be simplified. The output carry expression (C out ) is reduced as indicated.

23. Example 3: Function of Combinational Logic. Implement the two expressions that result from the previous example using AND-OR logic gates.

24. Solution: Function of Combinational Logic. These two expressions are implemented with AND-OR logic as shown in the following Figure to form a complete full-adder.